Michael H. Ayliffe

Design rules for highly parallel free-Space optical interconnects

Recently, a number of successful free-space chip-to-chip and board-to-board optical interconnects have been demonstrated. Here, we present some of the design rules that can be derived as a result of this work and also as a result of numerical and theoretical analyzes. We draw a number of conclusions. In the area of optoelectronic very large scale integration (VLSI) design, we suggest that differential electrical and optical transceiver designs provide the best performance. In the area of optical design, we present scaling and system partitioning laws for clustered optical relays and determine the interconnect distances at which microlens or macrolens systems are more suitable. We also show that the ease with which two modules can be aligned can be related to the optical invariant of the system and is, thus, a function of the size of the detector and the numerical aperture of the detector optics. Finally, we show that when multiple optical components must be aligned, very high individual component tolerances are required if the system as a whole is to have a high chance of success.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design, implementation, and characterization of a hybrid optical interconnect for a four-stage free-space optical backplane demonstrator

A four-stage unidirectional ring free-space optical interconnect system was designed, analyzed, implemented, and characterized. The optical system was used within a complementary metal-oxide semiconductor-self-electro-optic-effect-device-based optical backplane demonstrator that was designed to fit into a standard VME chassis. This optical interconnect was a hybrid microlens-macrolens system, in which the microlens relays were arranged in a maximum lens-to-waist configuration to route the optical beams from the optical power supply to the transceiver arrays, while the macrolens optical relays were arranged in a telecentric configuration to route optical signal beams from stage to stage. The following aspects of the optical system design are discussed: the optical parameters for the hybrid optical system, the image mapping of the two-dimensional array of optical beams from stage to stage, the alignment tolerance of the hybrid relay system, and the power budget of the overall optical interconnect. The implementation of the optical system, including the characterization of optical components, subsystem prealignment, and final system assembly, is presented. The two-dimensional array of beams for the stage-to-stage interconnect was adjusted with a rotational error of <0.05 degrees and a lateral offset error of <3.5 mum. The measured throughput is in good agreement with the lower-bound predictions obtained in the theoretical results, with an optical power throughput of -20.2 dB from the fiber input of the optical power supply to the modulator array and -25.5 dB from the fiber input to the detector plane.

A hybrid-SEED smart pixel array for a four-stage intelligent optical backplane demonstrator

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.

4x4 Vertical-Cavity-Surface- Emitting Laser (VCSEL) and Metal-Semiconductor-Metal (MSM) Optical Backplane Demonstrator System

We describe a system demonstrator based on vertical-cavity surface-emitting lasers, metal-semiconductor-metal detectors, printed circuit board (PCB) level optoelectronic device packaging, a compact bulk optical relay, and novel barrel/PCB optomechanics. The entire system was constructed in a standard VME electrical backplane chassis and was capable of operating at >1.7 Gbit/s of aggregate data capacity. In addition to the component technologies developed, we describe operational testing and characterization of the demonstrator.

Electrical, thermal and optomechanical packaging of large 2D optoelectronic device arrays for free-space optical interconnects

Innovative approaches to the design of a high-performance package module accommodating a array of surface-active devices indium bump bonded to a VLSI chip are presented. Electrical, thermal and optomechanical design considerations are discussed and experimental performance results of a prototype implementation are described. The package module supports 139 impedance-controlled signal connections as well as active temperature stabilization of the optoelectronic VLSI chip. The package module is compact, simple to assemble, alignment-tolerant and can be passively inserted into a free-space optical system with no need for further adjustments.

Design, implementation, and characterization of a kinematically aligned, cascaded spot- array generator for a modulator-based free-space optical interconnect

The design and the implementation of a modular spot-array generator for a modulator-based free-space optical interconnect is presented. Two cascaded diffractive optical elements produce 4 x 8 clusters on a 1600 microm x 800 microm pitch, where each cluster is a 4 x 4 array of (1/e(2)) 13.1-microm-radius spots on a 90-microm pitch. The spot-array generator is kinematically aligned to the interconnect system such that no realignment is necessary between removal and reinsertion. Characterization results are presented.

Implementation of a compact, four-stage, scalable optical interconnect for photonic backplane applications

We report on the implementation of a dense 512-beam free-space optical interconnect linking four optoelectronic VLSI chips at the backplane level. The system presented maximizes the positioning tolerances of the components by use of slow f-number (f/16) Gaussian beams and oversized apertures. A beam-clustering scheme whereby a 4 × 4 array of beams is transmitted by each minilens is used to provide a high channel density. A modular approach is used to decrease the number of degrees of freedom in the system and achieve passive alignment of the modules in the final integration phase. A design overview as well as assembly and experimental results are presented.

Optomechanical, electrical, and thermal packaging of large 2D optoelectronic device arrays for free-space optical interconnects

Photonics Systems GroupMcGill University, Department ofElectrical and Computer Engineering3480 University St., Montreal, Quebec, Canada, H3A 2A 7tel: (514) 398 2531, fax: (514) 398 3127, e-mail: mikeaphotonics.ece.mcgill.caI Was with McGill University Electrical and Computer Engineering Department,now with the Department ofPhysics at Heriot-Watt University, Scotland.

Six-degrees-of-freedom alignment of two-dimensional array components by use of off-axis linear Fresnel zone plates

A novel six-degrees-of-freedom (six-DOFs) alignment technique for assembling two-dimensional array components is presented. The technique uses off-axis linear Fresnel zone plates on one component that are combined with alignment targets on the other. The technique is compact and sensitive to all six DOFs; it was used to package an array of microlenses with a 32 x 32 array of GaAs multiple-quantum-well modulators flip-chip bonded to a 9 mm x 9 mm complementary-metal-oxide-semiconductor chip. By use of interference fringes to control the tilt misalignment, the worst-case misalignment of the microlenses relative to the chip is calculated to be as follows: lateral = 3.0 mum, rotational = 0.023 degrees , longitudinal = 13 mum, and tilt = 0.022 degrees . We also propose alternative implementations of the technique, including one that uses on-chip photodetectors to automate this six-DOF alignment technique.