D. Ravelosona

Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design.

Strain-controlled magnetic domain wall propagation in hybrid piezoelectric/ferromagnetic structures

The control of magnetic order in nanoscale devices underpins many proposals for integrating spintronics concepts into conventional electronics. A key challenge lies in finding an energy-efficient means of control, as power dissipation remains an important factor limiting future miniaturization of integrated circuits. One promising approach involves magnetoelectric coupling in magnetostrictive/piezoelectric systems, where induced strains can bear directly on the magnetic anisotropy. While such processes have been demonstrated in several multiferroic heterostructures, the incorporation of such complex materials into practical geometries has been lacking. Here we demonstrate the possibility of generating sizeable anisotropy changes, through induced strains driven by applied electric fields, in hybrid piezoelectric/spin-valve nanowires. By combining magneto-optical Kerr effect and magnetoresistance measurements, we show that domain wall propagation fields can be doubled under locally applied strains. These results highlight the prospect of constructing low-power domain wall gates for magnetic logic devices.

Reducing the critical current for spin-transfer switching of perpendicularly magnetized nanomagnets

We describe nanopillar spin valves with perpendicular anisotropy designed to reduce the critical current needed for spin transfer magnetization reversal while maintaining thermal stability. By adjusting the perpendicular anisotropy and volume of the free element consisting of a [Co/Ni] multilayer, we observe that the critical current scales with the height of the anisotropy energy barrier and we achieve critical currents as low as 120 μA in quasistatic room-temperature measurements of a 45 nm diameter device. The field-current phase diagram of such a device is presented.

Chemical order induced by ion irradiation in FePt (001) films

We demonstrate that the long-range order parameter S of sputtered FePt (001) films may be improved by using postgrowth He ion irradiation. This was demonstrated both on disordered (S∼0) and partially ordered (S∼0.4) films in which S was increased up to 0.3 and 0.6, respectively. X-ray diffraction analysis showed that these changes are due to irradiation-induced chemical ordering. The changes in the magnetic hysteresis loops correlate with the expected perpendicular magnetic anisotropy increase. This method may find applications in ultrahigh-density magnetic recording.

Perpendicular-magnetic-anisotropy CoFeB racetrack memory

Current-induced domain wall motion in magnetic nanowires drives the invention of a novel ultra-dense non-volatile storage device, called “racetrack memory.” Combining with magnetic tunnel junctions write and read heads, CMOS integrability and fast data access speed can also be achieved. Recent experimental progress showed that perpendicular-magnetic anisotropy (PMA) CoFeB could be a good candidate to build up racetrack memory and promise high performance like high-density (e.g., ∼1 F2/bit), fast-speed, and low-power beyond classical spin transfer torque memories. In this paper, we first present the design of PMA CoFeB racetrack memory and a spice-compatible model to perform mixed simulation with CMOS circuits. Its area, speed, and power dissipation performance has been simulated and evaluated based on different technology nodes.

Nanoscale imaging and control of domain-wall hopping with a nitrogen-vacancy center microscope

Observing jumping domain walls Domain walls, which separate regions of opposite magnetization in a ferromagnet, have rich dynamics that are difficult to characterize in small samples. Tetienne et al. imaged the magnetization of a thin ferromagnetic wire and observed the jumping of a domain wall between different positions along the wire. They used a scanning magnetic microscope based on a defect in diamond. The laser light needed to operate the microscope also enabled the control of the domain wall motion by causing local heating, which made the illuminated position more likely to contain a domain wall. Science, this issue p. 1366 A microscope based on a single spin of a diamond defect is used to observe magnetism dynamics. The control of domain walls in magnetic wires underpins an emerging class of spintronic devices. Propagation of these walls in imperfect media requires defects that pin them to be characterized on the nanoscale. Using a magnetic microscope based on a single nitrogen-vacancy (NV) center in diamond, we report domain-wall imaging on a 1-nanometer-thick ferromagnetic nanowire and directly observe Barkhausen jumps between two pinning sites spaced 50 nanometers apart. We further demonstrate in situ laser control of these jumps, which allows us to drag the domain wall along the wire and map the pinning landscape. Our work demonstrates the potential of NV microscopy to study magnetic nano-objects in complex media, whereas controlling domain walls with laser light may find an application in spintronic devices.

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes.

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I > Ico) and Neel-Brown model (I <; 0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication.

The nature of domain walls in ultrathin ferromagnets revealed by scanning nanomagnetometry.

The capacity to propagate magnetic domain walls with spin-polarized currents underpins several schemes for information storage and processing using spintronic devices. A key question involves the internal structure of the domain walls, which governs their response to certain current-driven torques such as the spin Hall effect. Here we show that magnetic microscopy based on a single nitrogen-vacancy defect in diamond can provide a direct determination of the internal wall structure in ultrathin ferromagnetic films under ambient conditions. We find pure Bloch walls in Ta/CoFeB(1 nm)/MgO, while left-handed Néel walls are observed in Pt/Co(0.6 nm)/AlOx. The latter indicates the presence of a sizable interfacial Dzyaloshinskii-Moriya interaction, which has strong bearing on the feasibility of exploiting novel chiral states such as skyrmions for information technologies.

Self-Enabled “Error-Free” Switching Circuit for Spin Transfer Torque MRAM and Logic

Spin transfer torque (STT) is one of the most promising switching approaches for magnetic tunnel junction (MTJ) nanopillars to build up innovative nonvolatile memory and logic circuits. It presents low critical current (e.g., <; 100 μA at 65 nm), simple switching scheme, and fast-speed; however, it suffers from a number of reliability issues like stochastic switching effects, process voltage temperature (PVT) variations, and erroneous reading etc. The mainstream solution is to enlarge the write pulse duration to reduce error rate, which sacrifices the speed and low power advantages. In this paper, we present a new switching circuit for STT memory and logic, allowing “error-free” as the switching operation becomes deterministic benefiting from the self-enabled mechanism. The switching power efficiency can be also improved thanks to a shorter switching duration. By using an accuracy spice model of STT-MTJ and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its high-reliable write/read operations and evaluate its potential area, power, and speed performance.