D. S. Ang

Reassessing the Mechanisms of Negative-Bias Temperature Instability by Repetitive Stress/Relaxation Experiments

A major intrinsic limitation of the reaction-diffusion (R-D) model for negative-bias temperature instability (NBTI) is revealed through dynamic stress experiments. We found no evidence of self-limiting recovery, one of the key features of the transport-based R-D model, after repeating the stress and relaxation cycles alternately for many times. The amount of recovery per cycle of the parameter of interest (e.g., threshold voltage shift, change in the charge-pumping (CP) current, etc.) is shown to remain constant, independent of the number of stress/recovery cycles. Under repeated cycling of the test device between stress and recovery, it is also found that the amount of parametric shift induced by the stress cycle becomes nearly identical to that recovered during the relaxation cycle, i.e., the parametric evolution under a fixed set of stress and recovery intervals is cyclic in nature. In conjunction with the thermal activation result, this cyclic behavior of the dynamic NBTI is ascribed to an ensemble of switching hole traps having broad spectra of characteristic trapping and detrapping time constants. The same group of traps responds under a fixed set of experimental conditions, giving rise to the cyclic behavior. The interface state generation was also investigated using a CP current measurement and is found to be permanent within the range of timing examined. It is also shown that the variation in the power-law exponent of the as-measured change in the CP current with temperature could be consistently explained by considering the different thermal activation of the hole trapping and interface state components. In view of these new evidences, previous claims of consistency between the generation/recovery of the interface states and the R-D model or its dispersive counterpart must be reviewed.

Ultrafast Measurement on NBTI

We combine customary pulsed I- V setup with a simple linear drain-current correction method to provide a possible standard for NBTI characterization. The method is implemented using standard equipment and yet is able to achieve sub-100-ns delay, the shortest reported to date for a wafer-level setup. Unlike the ramped-voltage method for which synchronization of the gate and drain waveforms is critical, relative delay between the gate and drain signals is not a concern in our case since measurement is made during quasi-steady state. For the present setup, gate and drain signals are shown to ldquostabilizerdquo after ~50 ns (upon switching) for a gate capacitive load of 1.5 pF (equivalent to ~80 devices used in this letter), rendering parallel testing possible using a single gate voltage source. Extension of the method for direct threshold voltage extraction by the constant subthreshold drain current approach is also discussed.

A novel subthreshold slope technique for the extraction of the buried-oxide interface trap density in the fully depleted SOI MOSFET

A novel experimental technique, based on the double-gate operation, is proposed for extracting the back interface trap density of the fully depleted SOI MOSFET. The method relies on simple current-voltage measurements, requires no prior knowledge of the silicon film thickness, and successfully eliminates inaccuracies arising from thickness variations of the accumulation layer, by maintaining both interfaces in depletion. The sensitivity of the technique is shown to depend on the ratio of the interface trap and oxide capacitances of the buried oxide, and is thus limited only by the buried oxide thickness. The technique has been successfully used to monitor the increase in back interface trap density following Fowler-Nordheim stress.

Mechanism of high-k dielectric-induced breakdown of the interfacial SiO 2 layer

A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO2 layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.

On the evolution of the recoverable component of the SiON, HfSiON and HfO 2 P-MOSFETs under dynamic NBTI

The evolution of the recoverable (R) component of negative-bias temperature instability (NBTI) is examined, as a function of the number of stress and relaxation cycles, for the SiON, HfSiON, and HfO2 p-MOSFETs. At typical NBTI oxide fields (∼7 MV/cm), a steady and substantial decrease of the R component in the case of the HfO2 p-MOSFET is observed, while the R component of the SiON and HfSiON p-MOSFETs are found to remain constant. A decrease in the R component of the SiON and HfSiON p-MOSFETs is observed only at much higher oxide fields (> 10 MV/cm). Evidence shows that the decrease in the R component is due to a greater tendency for the hole traps in the HfO2 to be transformed into a permanent form (P) under a given oxide field. The result therefore implies that, under typical NBTI oxide fields, the R and P components could share a common defect origin in the case of the HfO2 p-MOSFET. On the other hand, the R and P components are likely to have originated from different defect precursors in the case of the SiON and HfSiON p-MOSFETs. The existence of different oxide fields at which the transformation of the R component into a permanent form occurs for different gate dielectrics implies that the nature of the defect precursors responsible for the R component is intrinsic to the gate dielectric material.

Separation of Hole Trapping and Interface-State Generation by Ultrafast Measurement on Dynamic Negative-Bias Temperature Instability

Hole trapping and interface-state components of negative-bias temperature instability (NBTI)-induced threshold-voltage shift are separated via ultrafast switching measurement. Based on the phenomenological observation that dynamic NBTI is determined by a cyclic hole trapping/detrapping mechanism and that interface-state generation is relatively permanent, the time dependence of hole trapping during stress is precisely determined and then subtracted from the overall degradation of the first cycle to yield the time dependence of interface-state generation. Interface-state generation is shown to exhibit power-law time dependence with an initial exponent of ~0.5, which subsequently decreases to a steady value of 0.25 after ~1000 s at the stress condition studied (oxide field ~9 MV/cm). This evolution is shown to be consistent to that obtained via the charge-pumping method, confirming the underlying principle of the approach.

On the cyclic threshold voltage shift of dynamic negative-bias temperature instability

Based on new experimental evidence for the cyclical threshold voltage shift (ΔVt) under dynamic NBTI and a recent ab-initio study on the oxygen vacancy defects (hole traps) in the SiO2, an improved physical hole-trapping model for dynamic NBTI involving the Eδ∲ center is proposed. This model stipulates that the hole-trap precursor (i.e. the Si-Si dimer) responsible for the cyclic ΔVt only undergoes marginal structural relaxation under typical NBTI stress condition, such that the Si-Si bond is completely re-formed when the stress is terminated. This framework is subtly different from an existing one based on the earlier HDL model. The latter assumes that the switching hole traps are oxygen vacancy defects that have undergone significant structural relaxation and that the switching behavior is due to the repetitive transitions between the positively charged state and the charge-compensated state. Experimental results obtained from higher oxide-field stressing in fact do not support this proposition.

Effect of Hole-Trap Distribution on the Power-Law Time Exponent of NBTI

This letter presents a phenomenological relationship between the energy distribution of stress-induced hole traps and the power-law time exponent of NBTI. Experimental results show that increased generation of deep-level hole traps (DLHTs), i.e., trap-energy levels are near and/or above the Si conduction-band edge, yields a small exponent (< 0.2). Annealing the DLHTs results in the exponent increasing to ~ 0.3. Measurement on the n-MOSFET (in which the effect of DLHTs is suppressed) shows an exponent of ~0.4-0.5 for interface-state generation. This implies that the relatively small exponent (~0.3) of the p-MOSFET is due to remnant DLHTs which charge-up positively again when subjected to negative gate biasing during measurement. This new insight calls for a reexamination of the notion that as-measured exponents of ~0.14-0.17 are experimental proof of H2-diffusion-driven interface-state generation.

Evolution of Hole Trapping in the Oxynitride Gate p-MOSFET Subjected to Negative-Bias Temperature Stressing

We present experimental evidence of a thermally activated transformation of negative-bias-temperature-stress-induced transient hole trapping at preexisting oxide traps into more permanent trapped holes in the ultrathin oxynitride gate p-MOSFET. The transformation is also shown to correlate with the generation of stress-induced leakage current, indicating that it is one of the key mechanisms of bulk trap generation. A similar observation (reported elsewhere) applies to the HfO2 gate p-MOSFET, implying that the observed hole-trap transformation is a common mechanism for bulk trap generation across different gate oxide technologies. The results further imply that preexisting oxide defects, usually deemed irrelevant to negative-bias temperature instability, have a definite role on long-term device parametric drifts.

Capacitance Hysteresis in the High-k/Metal Gate-Stack From Pulsed Measurement

An unusual hysteresis is observed while measuring the capacitance-voltage (C-V) curve of the high-k/metal gate-stack using a pulsed-voltage technique. The hysteresis is found to vary only with the voltage ramp rate but not with the voltage pulse width. The C-V curve derived from the negative-to-positive (forward) voltage ramp has a consistently more positive flat ba5412279nd voltage than that obtained by the positive-to-negative (reverse) voltage ramp. The relative positions of the forward and reverse C-V curves are opposite to those measured using the quasi-static voltage-sweep method. Charge trapping/detrapping in the high-k oxide could not consistently account for these observations. An alternative explanation based on the lag in interface dipole response is proposed.