K. L. Pey

A study of thermo-mechanical stress and its impact on through-silicon vias

The BOSCH etch process, which is commonly used in microelectromechanical system fabrication, has been extensively investigated in this work for implementation in through-silicon via (TSV) technology for 3D-microsystems packaging. The present work focuses on thermo-mechanical stresses caused by thermal loading due to post-TSV processes and their impact on the electrical performance of through-silicon copper interconnects. A test vehicle with deep silicon copper-plated comb structure was designed to study and evaluate different deep silicon via etch processes and its effect on the electrical leakage characteristics under various electrical and thermal stress conditions. It has been shown that the leakage current between the comb interconnect structures increases with an increase in sidewall roughness and that it can be significantly lowered by smoothening the sidewalls. It was also shown that by tailoring a non-BOSCH etch process with the normal BOSCH process, a similar leakage current reduction can be achieved. It was also shown through thermo-mechanical simulation studies that there is a clear correlation between high leakage current behavior due to non-uniform Ta barrier deposition over the rough sidewalls and the thermo-mechanical stress induced by post-TSV processes.

The nature of dielectric breakdown

Dielectric breakdown is the process of local materials transiting from insulating to conductive when the dielectric is submerged in a high external electric field environment. We show that the atomistic changes of the chemical bonding in a nanoscale breakdown path are extensive and irreversible. Oxygen atoms in dielectric SiO2 are washed out with substoichiometric silicon oxide (SiOx with x<2) formation, and local energy gap lowering with intermediate bonding state of silicon atoms (Si1+, Si2+, and Si3+) in the percolation leakage path. Oxygen deficiency within the breakdown path is estimated to be as high as 50%–60%.

Vertically arrayed Si nanowire/nanorod-based core-shell p-n junction solar cells

Vertically arrayed Si nanowire/nanorod-based core-shell p-n junction solar cells have been fabricated by a solid-state phosphorus diffusion to convert the shell of the boron-doped p-type Si nanowires to n-type, thus forming a core-shell p-n junction structure. The nanowires with a nanosphere defined diameter were fabricated by an Au-film assisted electrochemical etching method, enabling controlled junction formation. The Si nanowire arrays show superior optical properties over a wide range of spectrum. In addition, longer nanowires are more effective for light trapping and absorption which is more advantageous for efficient energy harvesting. The cells show a high energy conversion efficiency of 1.47%, a significant improvement from the previously reported Si nanowire-based core-shell junction solar cells where the core-shell junctions were formed by an oppositely doped Si deposition on preformed Si nanowires. The relatively high efficiency might be mainly attributed to the extremely low reflectivity of t...

A High-Yield

In this letter, a resistive random access memory based on Ni electrode/HfOx, dielectric/n+ Si substrate structure is demonstrated, which can be integrated with Si diode as selector for application in crossbar architecture. The unipolar device shows well-behaved memory performance, such as high ON/OFF resistance ratio (>; 103), good retention characteristics (>; 105 s at 150 °C), satisfactory pulse switching endurance (>; 105 cycles), and a fast programming speed of about 50 ns. More importantly, it also exhibits almost 100% device yield on a 6-in wafer.

\hbox{HfO}_{x}

We study the influence of multiple oxygen vacancy traps in the percolated dielectric on the postbreakdown random telegraph noise (RTN) digital fluctuations in HfO2-based metal-oxide-semiconductor transistors. Our electrical characterization results indicate that these digital fluctuations are triggered only beyond a certain gate stress voltage. First-principles calculations suggest the oxygen vacancies to be responsible for the formation of a subband in the forbidden band gap region, which affects the triggering voltage (VTRIG) for the RTN fluctuations and leads to a shrinkage of the HfO2 band gap.

-Based Unipolar Resistive RAM Employing Ni Electrode Compatible With Si-Diode Selector for Crossbar Integration

In this paper, the thermal stability of TiN metal gate with various composition prepared by different preparation technology [(e.g., atomic layer deposition (ALD) or physical vapor deposition (PVD)] on HfO2 high-K dielectric is investigated and compared by physical and electrical analysis. After annealing of the TiN/HfO2 stack at 1000 °C for 30 s, it is observed that: (1) Nitrogen tends to out-diffuse from TiN for all the samples; (2) Oxygen from the interfacial layer (IL) between HfO2 and Si tends to diffuse toward TiN. PVD Ti-rich TiN shows a wider oxygen distribution in the gate stack, and a thinner IL than the N-rich sample. Ti penetration into HfO2 is also observed in the Ti-rich sample, which can potentially lead to the dielectric break-down. Besides, the oxygen out-diffusion can be significantly suppressed for ALD TiN compared to the PVD TiN samples.

Role of oxygen vacancies in HfO2-based gate stack breakdown

It has been shown that as the aspect ratio of through-silicon vias (TSV) increases, tapering of TSV structure greatly helps in achieving good sidewall coverage for dielectric, barrier and copper seed metal layers to eventually achieve a void-free copper via-filling by electroplating process. In the present work, a novel three-step tapered via etching process has been developed and demonstrated as a viable process for fabricating a void-free through-silicon copper interconnection structure. This paper discusses in great detail about the plasma etch mechanisms responsible for the step-by-step evolution of tapered silicon via the profile angle in the desirable range of 83–87°. It is further shown that the above multi-step etch process enables the formation of void-free copper vias for via depths close to 300 µm.

Thermal stability of TiN metal gate prepared by atomic layer deposition or physical vapor deposition on HfO2 high-K dielectric

The migration of Ta atoms from a transistor gate electrode into the percolated high-κ (HK) gate dielectrics is directly shown using transmission electron microscopy analysis. A nanoscale metal filament that formed under high current injection is identified to be the physical defect responsible for the ultrafast transient breakdown (BD) of the metal-gate/high-κ (MG/HK) gate stacks. This highly conductive metal filament poses reliability concerns for MG/HK gate stacks as it significantly reduces the post-BD reliability margin of a transistor.

The development of a tapered silicon micro-micromachining process for 3D microsystems packaging

Both unipolar and bipolar resistive switchings are demonstrated on NiSi gate transistors after gate dielectric percolation. Nanoscale Ni filaments and oxygen ion conduction are found in the percolation path as the physical defects responsible for resistive switching. Memory cells can be fabricated together with the metal gate transistors for ease of integration.

Direct visualization and in-depth physical study of metal filament formation in percolated high-κ dielectrics

Our results show that the defect distribution within a nanometer size percolation path is nonuniform. The defects, which are shown as oxygen vacancies, spread out radially from the center of the percolation path. The conduction band edges of the defective oxide are lowered for 0.14–0.78eV when the Si–O composition changes from SiO1.76 to SiO0.7.