D. Schmidt

SiGe HBT technology with f T /f max of 300GHz/500GHz and 2.0 ps CML gate delay

A SiGe HBT technology featuring fT/fmax/BVCEO=300GHz/500GHz/1.6V and a minimum CML ring oscillator gate delay of 2.0 ps is presented. The speed-improvement compared to our previous SiGe HBT generations originates from lateral device scaling, a reduced thermal budget, and changes of the emitter and base composition, of the salicide resistance as well as of the low-doped collector formation.

Novel collector design for high-speed SiGe:C HBTs

We describe a novel collector design for high-frequency SiGe:C HBTs without deep trenches and with low-resistance collectors formed by high-dose ion implantation after shallow trench formation. f/sub T/ values of 200 GHz at BV/sub CEO/=2.0 V and ring oscillator delays of 4.3 ps are obtained. Excellent static characteristics and high yield were achieved for the HBT module integrated in a 0.25 /spl mu/m CMOS platform.

SiGe:C BiCMOS technology with 3.6 ps gate delay

A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.

A complementary BiCMOS technology with high speed npn and pnp SiGe:C HBTs

We demonstrate SiGe:C pnp HBTs in a complementary bipolar CMOS flow with f/sub T//f/sub max/ values of 80 GHz/120 GHz at BV/sub CEO/ = 2.6 V and a ring oscillator delay of 8.9 ps. The simultaneously fabricated npn HBTs sustain no significant performance loss compared to the npn-only BiCMOS, confirmed by f/sub T//f/sub max/ values of 180 GHz/185 GHz and a ring oscillator delay of 4.6 ps. A pnp-only BiCMOS flow produces peak f/sub T//f/sub max/ values for pnp devices of 115 GHz/115 GHz. The high speed performance of the pnp transistors surpasses the best reported values of this transistor type substantially.

SiGe HBT module with 2.5 ps gate delay

We present a double-polysilicon SiGe:C HBT module showing a CML ring oscillator (RO) gate delay tau of 2.5 ps, and fT/ fmax/BVCEo values of 300 GHz/350 GHz/1.85V. A key new feature of the HBT module is a connection of the extrinsic and intrinsic base regions by lateral epitaxial overgrowth. This facilitates simultaneously a very low base resistance and a reduced base-collector capacitance. In addition, the RF performance is enhanced for devices rotated by 45deg with respect to the standard orientation due to favorable epitaxial growth behavior.

SiGe BiCMOS Technology with 3.0 ps Gate Delay

This work reports on a 130 nm BiCMOS technology with high-speed SiGe:C HBTs featuring a transit frequency of 255 GHz and a maximum oscillation frequency of 315 GHz at an emitter area of 0.17 x 0.53 mum². A minimum gate delay of 3.0 ps was achieved for CML ring oscillators. Breakdown voltages of the HBTs are measured to be BV_CEO=1.8 V, BV_CBO=5.6 V, andBV_EBO=1.9 V.

The impact of channel engineering on the performance and reliability of LDMOS transistors

In this paper, we study the performance and reliability of LDMOS (laterally diffused MOS) transistors, developed in a 0.25/spl mu/m SiGe:C BiCMOS technology, for two different channel doping schemes a) uniform and b) single-sided halo (SH). We show that SH LDMOS transistors are more reliable and offer better DC and high frequency performance. We also demonstrate BV/sub DS/ *F/sub t/ values up to 630GHzV with SH LDMOS transistors.

Integration of high-performance SiGe:C HBTs with thin-film SOI CMOS

A new scheme for the integration of high-performance HBTs with thin-film SOI CMOS is demonstrated. The thickness incompatibility problem of thin-body SOI CMOS and high-performance SiGe HBTs is solved by forming HBTs on silicon islands in the BOX. Low-resistance collector wells are realized by ion implantation into the SOI substrate. SiGe:C HBTs with f/sub T//f/sub max/ values of 220 GHz/230 GHz and a BV/sub CEO/ of 2.0 V and fully-depleted CMOS transistors with 90 nm gate length are fabricated on SOI wafers with 30 nm Si thickness.

SiGe HBT with fx/fmax of 505 GHz/720 GHz

An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.