Nihar R. Mohapatra

The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K/sub gate/ for different target subthreshold leakage currents has been identified.

32nm high-density high-speed T-RAM embedded memory technology

Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process with read and write times of 1ns and a bit fail rate less than 0.5ppm is reported for the first time. T-RAM memory cell median read current of 250µA/cell at 1.2V with an Ion/Ioff current ratio of more than 108 is demonstrated at 105°C. Robust margins to dynamic disturb due to the access (read/write) of neighboring bits in the memory array have also been verified.

CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters

The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.

Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics

This paper analyzes in detail the fringing induced barrier lowering (FIBL) in MOS transistors with high-k gate dielectrics using 2D device simulations. We found that the device short channel performance is degraded with increase in gate dielectric permittivity (K/sub gate/) due to an increase in the dielectric physical thickness to channel length ratio. For K/sub gate/ greater than K/sub si/, we observe a substantial coupling between source and drain regions through the gate insulator. This fact is validated by extensive device simulations with different channel length and overlap length over a wide range of dielectric permittivities. We also observe that the overlap length is an important parameter for optimizing DC performance in short channel MOS transistors. The effect of stacked gate dielectric and lateral channel engineering on the performance of high-k gate dielectric MOS transistors is also studied to substantiate the above observations.

The impact of channel engineering on the performance and reliability of LDMOS transistors

In this paper, we study the performance and reliability of LDMOS (laterally diffused MOS) transistors, developed in a 0.25/spl mu/m SiGe:C BiCMOS technology, for two different channel doping schemes a) uniform and b) single-sided halo (SH). We show that SH LDMOS transistors are more reliable and offer better DC and high frequency performance. We also demonstrate BV/sub DS/ *F/sub t/ values up to 630GHzV with SH LDMOS transistors.

Fast and accurate lithography simulation using cluster analysis in resist model building

Abstract. As technology nodes continue to shrink, optical proximity correction (OPC) has become an integral part of mask design to improve the subwavelength printability. The success of lithography simulation to perform OPC on an entire chip relies heavily on the performance of lithography process models. Any small enhancement in the performance of process models can result in a valuable improvement in the yield. We propose a robust approach for lithography process model building. The proposed scheme uses the clustering algorithm for model building and thereby improves the accuracy and computational efficiency of lithography simulation. The effectiveness of the proposed method is verified by simulating some critical layers in 14- and 22-nm complementary metal oxide semiconductor technology nodes. Experimental results show that compared with a conventional approach, the proposed method reduces the simulation time by 50× with ∼5% improvement in accuracy.

Integration of high-performance SiGe:C HBTs with thin-film SOI CMOS

A new scheme for the integration of high-performance HBTs with thin-film SOI CMOS is demonstrated. The thickness incompatibility problem of thin-body SOI CMOS and high-performance SiGe HBTs is solved by forming HBTs on silicon islands in the BOX. Low-resistance collector wells are realized by ion implantation into the SOI substrate. SiGe:C HBTs with f/sub T//f/sub max/ values of 220 GHz/230 GHz and a BV/sub CEO/ of 2.0 V and fully-depleted CMOS transistors with 90 nm gate length are fabricated on SOI wafers with 30 nm Si thickness.

Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs

The effect of programming biases on the cycling endurance of NOR flash EEPROMs is studied under CHE and CHISEL operation. CHE degradation increases at higher control gate bias (V/sub CG/) and is insensitive to changes in drain bias (V/sub D/) CHISEL degradation is insensitive to changes in both V/sub CG/, and V/sub D/. Furthermore, CHISEL always shows lower degradation when compared to CHE under identical bias and similar programming time. The possible physical mechanisms responsible for the above behavior are clarified by using full band Monte-Carlo simulations.

Application of look-up table approach to high-K gate dielectric MOS transistor circuits

In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an excellent match between LUT simulator and mixed mode simulations using MEDICI. This work clearly demonstrates the predictive power of the new simulator, as it enables evaluation of circuits directly from device simulation results without going through model parameter extraction.

The Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance

The potential impact of high permittivity gate dielectrics 0n the circuit performance is studied over a wide range of gate dielectrics using 2-Dimensional device and monte-carlo simulations. It is found that there is a decrease in parasitic outer fringe capacitance, gate to channel capacitance and all increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by high-K gate dielectrics. The lower parasitic outer fringe capacitance is beneficial in reducing the circuit delay, while an increase in internal fringe capacitance and decrease in gate to channel capacitance will degrade the gain, power dissipation and noise margin of the circuit. AIso, from the circuit point of view, at the 70nm technology generation, the presence of all optimum K gate for different sub-threshold leakage currents has been identified.