D. Soler

Stability of hydrogenated nanocrystalline silicon thin-film transistors

Abstract Hydrogenated nanocrystalline silicon thin-films were obtained by catalytic chemical vapour deposition at low substrate temperatures (150°C) and high deposition rates (10 A/s). These films, with crystalline fractions over 90%, were incorporated as the active layers of bottom-gate thin-film transistors. The initial field-effect mobilities of these devices were over 0.5 cm2/V s and the threshold voltages lower than 4 V. In this work, we report on the enhanced stability of these devices under prolonged times of gate bias stress compared to amorphous silicon thin-film transistors. Hence, they are promising candidates to be considered in the future for applications such as flat-panel displays.

Analysis of bias stress on thin-film transistors obtained by Hot-Wire Chemical Vapour deposition

The stability under gate bias stress of unpassivated thin film transistors was studied by measuring the transfer and output characteristics at different temperatures. The active layer of these devices consisted of in nanocrystalline silicon deposited at 125°C by Hot-Wire Chemical Vapour Deposition. The dependence of the subthreshold activation energy on gate bias for different gate bias stresses is quite different from the one reported for hydrogenated amorphous silicon. This behaviour has been related to trapped charge in the active layer of the thin film transistor.

Optimisation of doped microcrystalline silicon films deposited at very low temperatures by hot-wire CVD

Abstract In this paper we present new results on doped μc-Si:H thin films deposited by hot-wire chemical vapour deposition (HWCVD) in the very low temperature range (125–275°C). The doped layers were obtained by the addition of diborane or phosphine in the gas phase during deposition. The incorporation of boron and phosphorus in the films and their influence on the crystalline fraction are studied by secondary ion mass spectrometry and Raman spectroscopy, respectively. Good electrical transport properties were obtained in this deposition regime, with best dark conductivities of 2.6 and 9.8 S cm −1 for the p- and n-doped films, respectively. The effect of the hydrogen dilution and the layer thickness on the electrical properties are also studied. Some technological conclusions referred to cross contamination could be deduced from the nominally undoped samples obtained in the same chamber after p- and n-type heavily doped layers.

Electronic transport in low temperature nanocrystalline silicon thin-film transistors obtained by hot-wire CVD

Hydrogenated nanocrystalline silicon (nc-Si:H) obtained by hot-wire chemical vapour deposition (HWCVD) at low substrate temperature (150 °C) has been incorporated as the active layer in bottom-gate thin-film transistors (TFTs). These devices were electrically characterised by measuring in vacuum the output and transfer characteristics for different temperatures. The field-effect mobility showed a thermally activated behaviour which could be attributed to carrier trapping at the band tails, as in hydrogenated amorphous silicon (a-Si:H), and potential barriers for the electronic transport. Trapped charge at the interfaces of the columns, which are typical in nc-Si:H, would account for these barriers. By using the Levinson technique, the quality of the material at the column boundaries could be studied. Finally, these results were interpreted according to the particular microstructure of nc-Si:H.

Microdoping compensation of microcrystalline silicon obtained by hot-wire chemical vapour deposition

Abstract Undoped hydrogenated microcrystalline silicon was obtained by hot-wire chemical vapour deposition at different silane-to-hydrogen ratios and low temperature (

Investigations on doping of amorphous and nanocrystalline silicon films deposited by catalytic chemical vapour deposition

Hydrogenated amorphous and nanocrystalline silicon, deposited by catalytic chemical vapour deposition, have been doped during deposition by the addition of diborane and phosphine in the feed gas, with concentrations in the region of 1%. The crystalline fraction, dopant concentration and electrical properties of the films are studied. The nanocrystalline films exhibited a high doping efficiency, both for n and p doping, and electrical characteristics similar to those of plasma-deposited films. The doping efficiency of n-type amorphous silicon is similar to that obtained for plasma-deposited electronic-grade amorphous silicon, whereas p-type layers show a doping efficiency of one order of magnitude lower. A higher deposition temperature of 450°C was required to achieve p-type films with electrical characteristics similar to those of plasma-deposited films.

Substrate influence on the properties of doped thin silicon layers grown by Cat-CVD

We present structural and electrical properties for p- and n-type layers grown close to the transition between a-Si:H and nc-Si:H onto different substrates: Corning 1737 glass, ZnO:Al-coated glass and stainless steel. Structural properties were observed to depend on the substrate properties for samples grown under the same deposition conditions. Different behaviour was observed for n- and p-type material. Stainless steel seemed to enhance crystallinity when dealing with n-type layers, whereas an increased crystalline fraction was obtained on glass for p-type samples. Electrical conduction in the direction perpendicular to the substrate seemed to be mainly determined by the interfaces or by the existence of an amorphous incubation layer that might determine the electrical behaviour. In the direction perpendicular to the substrate, n-type layers exhibited a lower resistance value than p-type ones, showing better contact properties between the layer and the substrate.

Thin silicon films ranging from amorphous to nanocrystalline obtained by hot-wire CVD

In this paper, we have presented results on silicon thin films deposited by hot-wire CVD at low substrate temperatures (200°C). Films ranging from amorphous to nanocrystalline were obtained by varying the filament temperature from 1500 to 1800°C. A crystalline fraction of 50% was obtained for the sample deposited at 1700°C. The results obtained seemed to indicate that atomic hydrogen plays a leading role in the obtaining of nanocrystalline silicon. The optoelectronic properties of the amorphous material obtained in these conditions are slightly poorer than the ones observed in device-grade films grown by plasma-enhanced CVD due to a higher hydrogen incorporation (13%).

Nanocrystalline top-gate thin film transistors deposited at low temperature by hot-wire CVD on glass

n and p-type nanocrystalline thin film transistors in coplanar top gate configuration have been processed at low temperature. All silicon layers (intrinsic, n and p-type) have been deposited by hot-wire chemical vapor deposition on glass substrates covered with SiO/sub 2/. Gate insulation has been achieved by means of high quality sputtered SiO/sub 2/. The maximum temperature reached during the whole process was 200/spl deg/C. Very high field effect mobility has been obtained for both kinds of devices, with values of 22 cm V/sup -1/s/sup -1/ for the electron mobility and around 1.0 cm V/sup -1/s/sup -1/ for the hole mobility.

Heterojunction silicon solar cells obtained by hot-wire CVD at low temperature

In this work, first results on bifacial heterojunction solar cells incorporating thin silicon films by Hot-Wire CVD are presented. The heterojunction with intrinsic thin layer concept applied to the back contact avoids the high temperature anneal usually required for back surface field formation. Both p- and n-type crystalline silicon substrates have been considered. Contactless quasi-steady-state photoconductance measurements evidenced implicit open circuit voltages over 600 mV for heterojunction solar cells by HWCVD. Preliminary devices were fabricated with n-doped amorphous silicon emitter and p-doped microcrystalline silicon back contact. Intrinsic amorphous silicon buffer layers 5 nm thick were used in both sides. The maximum temperature in the whole fabrication process was 200 /spl deg/C. The best solar cell yielded an active area conversion efficiency of 9.8% with an open circuit voltage of 577 mV, short circuit current of 26.1 mA/spl middot/cm/sup -2/ and fill factor of 65%.