D. Zupac

Separation of effects of oxide-trapped charge and interface-trapped charge on mobility in irradiated power MOSFETs

An effective approach to separating the effects of oxide-trapped charge and interface-trapped charge on mobility degradation in irradiated MOSFETs is demonstrated. It is based on analyzing mobility data sets that have different functional relationships between the radiation-induced-oxide-trapped charge and interface-trapped charge. Separation of the effects of these two trapped charge components is only possible if they are not linearly dependent. A significant contribution of oxide-trapped charge to mobility degradation is demonstrated and quantified. >

Radiation-induced mobility degradation in p-channel double-diffused metal-oxide-semiconductor power transistors at 300 and 77 K

The effects of radiation‐induced interface‐trapped charge and oxide‐trapped charge on the inversion‐layer hole mobility in p‐channel double‐diffused metal‐oxide‐semiconductor power transistors at 300 and 77 K are investigated. The mobility degradation is more pronounced at 77 K than at 300 K, due to increased importance of Coulomb scattering from trapped charge when phonon scattering is significantly reduced. The mobility degradation is primarily due to interface‐trapped charge, but the effects of oxide‐trapped charge must be taken into account in order to properly describe the mobility behavior, particularly at cryogenic temperatures.

Effects of radiation‐induced oxide‐trapped charge on inversion‐layer hole mobility at 300 and 77 K

The effects of radiation‐induced interface‐trapped charge and oxide‐trapped charge on the inversion‐layer hole mobility in p‐channel double‐diffused metal‐oxide‐semiconductor transistors at 300 and 77 K are reported. The mobility degradation is more pronounced at 77 than at 300 K, due to an increased importance of Coulomb scattering from trapped charge when phonon scattering is significantly reduced. The mobility degradation is primarily due to interface‐trapped charge, but the effects of oxide‐trapped charge must be taken into account in order to properly describe the mobility behavior, particularly at cryogenic temperatures.

Application of test method 1019.4 to nonhardened power MOSFETs

The applicability of MIL-STD-883D Method 1019.4 to predicting the low-dose-rate radiation response of nonhardened power MOSFETs has been investigated. Method 1019.4 works well in providing bounds for the threshold-voltage shift. However, it is not intended to provide an estimate of the actual /spl Delta/V/sub T/ due to low-dose-rate irradiation. A modified method is proposed which can yield more information on the threshold-voltage shift at low dose rates for power MOSFETs. >

Comparison of 1/f noise in irradiated power MOSFETs measured in the linear and saturation regions

1/f noise in n-channel and p-channel power MOSFETs is investigated as a function of total dose and annealing. All the devices used in this study are nonhardened commercial parts. The preirradiation noise dependence on the gate and drain biases is analyzed. A different evolution of the noise measured in the linear and saturation regions through irradiation and annealing is reported. The build-up of interface traps was found to correlate well with the increase of noise during annealing for the p-channel devices. Measurements taken in the saturation region do not correlate as well with radiation-induced charge build-up, even though the overall noise increases slightly during irradiation. >

Determining the drain doping in DMOS transistors using the hump in the leakage current

The hump in the leakage current of double-diffused metal-oxide-semiconductor (DMOS) transistors observed for low drain voltages is explained. This hump is due to surface generation current of the gate-controlled diode formed by the base-drain p-n junction. The drain bias of the DMOS transistor is shown to have the same effect on the charge at the drain surface as the body bias in the conventional MOSFET. The body effect is used to develop a new method for determining the drain doping in DMOS transistors. This method is nondestructive, and does not require special test structures. Instead, electrical measurements are performed on conventional DMOS transistors. The method is ideally suited for determining the doping in the drain region of interest. Specifically, in DMOS transistors in which a surface implant is used to reduce the on-resistance, the method provides the doping concentration in the implanted region. In DMOS transistors which do not have the surface implant, the method yields the doping concentration in the drain epitaxial layer. In this study, the method is illustrated by determining the drain doping for six discrete power MOSFET device types from three different manufacturers. >

Comparison between the effects of positive noncatastrophic HBM ESD stress in n-channel and p-channel power MOSFETs

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain.<<ETX>>

Detection of ESD-induced noncatastrophic damage in p-channel power MOSFETs

Abstract Effects of noncatastrophic human body model (HBM) electrostatic discharge (ESD) stress at the gate of p -channel power MOSFETs (metal-oxide-semiconductor field-effect transistors) are examined. Low-level stress results in threshold voltage change due to ESD-induced charge injection and trapping in the gate oxide. High-level stress causes an increase in the drain-to-source leakage current due to thermal damage to the drain-body junction. The detection of this noncatastrophic damage may require measurements of leakage currents below 1 nA. Monitoring the subthreshold drain current of power MOSFETs is proposed as a reliable method of detecting the damage induced by high-level HBM ESD stress.

Annealing of ESD-induced damage in power MOSFETs

Abstract Annealing properties of ESD-induced noncatastrophic damage in power MOSFETs are reported. ESD stress results in positive charge trapping in the gate oxide and/or an increase in the drain-to-source leakage current. The annealing is very slow at room temperature and is significantly accelerated at elevated temperatures. The oxide-trapped charge density is a logarithmically decreasing function of anneal time. The rate of positive oxide-trapped charge anneal depends on the anneal temperature and on the charge density before anneal. The effect of electric field on room-temperature annealing is very small. The increased drain-to-source leakage does not change appreciably during anneal.

ESD effects in power MOSFETs: a review☆

Abstract Depending on the energy of the pulse, electrostatic discharge (ESD) may cause either catastrophic failure (gate-oxide breakdown) or non-catastrophic damage (degradation) of power MOSFETs. Non-catastrophic damage is manifested in the form of positive charge trapping in the gate oxide and increased drain-to-source leakage current. Low-level human body model (HBM) ESD stress causes uniform charge injection and trapping over the are of the device. High-level HBM ESD stress results in localized charge injection in both n-channel and p-channel power MOSFETs. However, the effects of this stress on n-channel power MOSFETs are different from those on p-channel MOSFETs.