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Featured researches published by K.F. Galloway.


IEEE Transactions on Nuclear Science | 1997

Hardness assurance testing of bipolar junction transistors at elevated irradiation temperatures

Steven C. Witczak; Ronald D. Schrimpf; Daniel M. Fleetwood; K.F. Galloway; R.C. Lacoe; D C. Mayer; James M. Puhl; R L. Pease; John S. Suehle

The effect of dose rate on radiation-induced current gain degradation was quantified for radiation-hardened poly-Si emitter n-p-n bipolar transistors over the range of 0.005 to 294 rad(Si)/s. Degradation increases sharply with decreasing dose rate and saturates near 0.005 rad(Si)/s. The amount of degradation enhancement at low dose rates decreases monotonically with total dose. In addition, the effect of ambient temperature on radiation-induced gain degradation at 294 rad(Si)/s was investigated over the range of 25 to 240/spl deg/C. Degradation is enhanced with increasing temperature while simultaneously being moderated by in situ annealing, such that, for a given total dose, an optimum irradiation temperature for maximum degradation results. The optimum irradiation temperature decreases logarithmically with total dose and, for a given dose, is smaller than optimum temperatures reported previously for p-n-p devices. High dose rate irradiation at elevated temperatures is less effective at simulating low dose rate degradation for the n-p-n transistor than for the p-n-p transistors. However, additional degradation of the n-p-n device at elevated temperatures is easily obtained using overtest. Differences in the radiation responses of the device types are attributed to the relative effects of oxide trapped charge on gain degradation. High dose rate irradiation near 125/spl deg/C is found to be suitable for the hardness assurance testing of these devices provided a design margin of at least two is employed.


IEEE Transactions on Nuclear Science | 1998

Space charge limited degradation of bipolar oxides at low electric fields

Steven C. Witczak; R.C. Lacoe; Donald C. Mayer; Daniel M. Fleetwood; Ronald D. Schrimpf; K.F. Galloway

P-type MOS capacitors fabricated in two bipolar processes were examined for ionizing radiation-induced threshold voltage shifts as a function of total dose, dose rate, temperature and bias. Hydrogen passivation of acceptor impurities near the Si surface was observed through decreases in the Si capacitance. The reduction in net electrically active dopants shifts the threshold voltage negative with total dose. The relative contribution of dopant passivation to the radiation-induced threshold voltage shift is most significant for irradiations performed under zero bias above 100/spl deg/C. For zero bias, dopant passivation and densities of radiation-induced interface traps and net positive oxide trapped charge all exhibit true dose rate and time dependent effects. A positive gate bias during irradiation eliminates the dose rate dependence. High dose rate irradiation at elevated temperatures enhances oxide degradation while simultaneously accelerating the annealing of damage. The enhancement in interface trap formation is greater than that of net positive oxide trapped charge and occurs over a greater range of temperatures. The temperature dependence of dopant passivation indicates that hydrogen transport through the oxides is accelerated with temperature. These results strongly suggest that metastably trapped charge in the oxide bulk reduces high dose rate degradation at room temperature by inhibiting the transport of holes and H/sup +/ ions.


IEEE Transactions on Nuclear Science | 1995

Comparison of ionizing-radiation-induced gain degradation in lateral, substrate, and vertical PNP BJTs

D.M. Schmidt; Daniel M. Fleetwood; Ronald D. Schrimpf; Ronald L. Pease; R.J. Graves; G.H. Johnson; K.F. Galloway; W.E. Combs

A comparison is presented of ionizing-radiation-induced gain degradation in lateral, substrate, and vertical PNPs. The dose-rate dependence of current gain degradation in lateral PNP BJTs is even stronger than the dependence previously reported for NPN BJTs. Various mechanisms are presented and their relative significance for gain degradation in the lateral, substrate, and vertical PNPs is discussed. A detailed comparison of the lateral and substrate PNP devices is given. The specific lateral and substrate devices considered here are fabricated in the same process and possess identical emitters. Even though these devices have identical emitters and undergo the same processing steps, the lateral devices degrade significantly more than the substrate devices.


IEEE Transactions on Nuclear Science | 1998

Moderated degradation enhancement of lateral pnp transistors due to measurement bias

Steven C. Witczak; Ronald D. Schrimpf; H. J. Barnaby; R.C. Lacoe; D.C. Mayer; K.F. Galloway; Ronald L. Pease; Daniel M. Fleetwood

Enhanced low-dose-rate gain degradation of ADI RF25 lateral pnp transistors is examined as a function of the bias at which the gain is measured. Degradation enhancement at low dose rates diminishes rapidly with increasing measurement bias between the emitter and the base. Device simulations reveal that interface trap charging, field effects from oxide trapped charge and emitter metallization, base series resistance and high-level carrier injection all contribute to this behavior. As a practical consequence, accelerated hardness assurance tests of this device require higher irradiation temperatures or larger design margins for low power applications.


IEEE Transactions on Nuclear Science | 1993

A conceptual model of a single-event gate-rupture in power MOSFETs

J.R. Brews; M. Allenspach; Ronald D. Schrimpf; K.F. Galloway; J.L. Titus; C.F. Wheatley

Proposes a physical model of hole-collection following a heavy-ion strike to explain the development of oxide fields sufficient to cause single-event gate rupture (SEGR) in power MOSFETs. It is found that the size of the maximum field and the time at which it is attained are strongly affected by the hole mobility. Oxide fields larger than the intrinsic breakdown strength of the oxide can arise from the holes collecting at the interface and their image charge in the gate electrode. These high fields persist for times of the order of picoseconds. It is not known how long these fields must persist to initiate SEGR. >


IEEE Transactions on Nuclear Science | 1996

A review of the techniques used for modeling single-event effects in power MOSFETs

G.H. Johnson; J.M. Palau; C. Dachs; K.F. Galloway; Ronald D. Schrimpf

Heavy ions can trigger catastrophic failure modes in power metal-oxide-semiconductor field-effect transistors (MOSFETs). Single-event effects (SEE), namely, single-event burnout (SEB), and single-event gate rupture (SEGR), of power MOSFETs are catastrophic failure mechanisms that are initiated by the passage of a heavy ion through the device structure. Various analytical, semianalytical, and simulation models have been developed to help explain these phenomena. This paper presents a review of these models and explains their merits and limitations. New results are included to illustrate the approaches.


IEEE Transactions on Nuclear Science | 1996

The determination of Si-SiO/sub 2/ interface trap density in irradiated four-terminal VDMOSFETs using charge pumping

S.C. Witczak; K.F. Galloway; Ronald D. Schrimpf; J.L. Titus; J.R. Brews; G. Prevost

The utility of charge pumping to measure Si-SiO/sub 2/ interface trap density in irradiated four-terminal VDMOSFETs is demonstrated. A modification of the conventional charge pumping approach is employed, where recombination of charge through interface traps in the neck region is measured in the drain. Three components of drain current resulting from the charge pumping measurement are identified. When the device is properly biased, charge pumping current can be separated from the other components of drain current and modeled over a wide range of interface trap densities using standard charge pumping theory. When sources of error are accounted for, radiation-induced interface trap densities measured with charge pumping are in good quantitative agreement with those estimated with the midgap charge separation and subthreshold hump techniques.


IEEE Transactions on Electron Devices | 1993

Simulating single-event burnout of n-channel power MOSFET's

G.H. Johnson; Jakob H. Hohl; Ronald D. Schrimpf; K.F. Galloway

Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs. >


IEEE Transactions on Nuclear Science | 2001

Heavy-ion-induced breakdown in ultra-thin gate oxides and high-k dielectrics

Lloyd W. Massengill; B.K. Choi; Daniel M. Fleetwood; Ronald D. Schrimpf; K.F. Galloway; M.R. Shaneyfelt; Timothy L. Meisenheimer; Paul E. Dodd; J.R. Schwank; Y.M. Lee; R. S. Johnson; Gerald Lucovsky

Presents experimental results on single-event-induced breakdown in sub-5-nm plasma-enhanced SiO/sub 2/, nitrided SiO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2/, and Zr/sub 0.4/Si/sub 1.6/O/sub 4/ dielectrics typical of current and future-generation commercial gate oxides. These advanced oxides are found to be quite resistant to ion-induced breakdown. Radiation-induced soft breakdown was observed in some films with 342 MeV Au (LET=80 MeV/mg/cm/sup 2/) but not 340 MeV I (LET=60 MeV/mg/cm/sup 2/). The critical voltage to hard breakdown was found to scale with the square root of the physical oxide thickness, not with the energy stored on the gate capacitance. Alternative dielectrics with equivalent oxide thickness substantially below their physical thickness were found to exhibit significantly higher voltage to hard breakdown than SiO/sub 2/ counterparts. All of the samples reached ion-induced hard breakdown at applied voltages well above typical operating power-supply voltages; these findings bode well for the use of advanced commercial integrated circuits in space systems.


IEEE Transactions on Nuclear Science | 1995

Impact of oxide thickness on SEGR failure in vertical power MOSFETs; development of a semi-empirical expression

J.L. Titus; C.F. Wheatley; D.I. Burton; I. Mouret; M. Allenspach; J.R. Brews; Ronald D. Schrimpf; K.F. Galloway; Ronald L. Pease

This paper investigates the role that the gate oxide thickness (T/sub ox/) plays on the gate and drain failure threshold voltages required to induce the onset of single-event gate rupture (SEGR). The impact of gate oxide thickness on SEGR is experimentally determined from vertical power metal-oxide semiconductor field-effect transistors (MOSFETs) having identical process and design parameters, except for the gate oxide thickness. Power MOSFETs from five variants were specially fabricated with nominal gate oxide thicknesses of 30, 50, 70, 100, and 150 nm. Devices from each variant were characterized to mono-energetic ion beams of Nickel, Bromine, Iodine, and Gold. Employing different bias conditions, failure thresholds for the onset of SEGR were determined for each oxide thickness. Applying these experimental test results, a previously published empirical expression is extended to include the effects of gate oxide thickness. In addition, observations of ion angle, temperature, cell geometry, channel conductivity, and curvature at high drain voltages are briefly discussed.

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D. Zupac

University of Arizona

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J.L. Titus

Naval Surface Warfare Center

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