Da-Cheng Juan

Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors

Network-on-Chips (NoCs) have emerged as the backbone for the inter-core communication of a chip-multiprocessor (CMP). This paper evaluates and analyzes the advantages of managing the processing cores and the on-chip communication fabric in synergy for the purpose of performance increase under power constraints. A semi-supervised reinforcement learning (RL) based approach is proposed for performing dynamic voltage and frequency scaling (DVFS) so as to enable the efficient usage of the available on-chip power budget while maximizing performance. The experimental results show that, on average, overall performance is increased by 11% under iso-power conditions, while a core-only or an uncore-only performance boosting approach can only achieve 7% and 3% improvement in performance, respectively.

A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors

Thermal issues have become critical roadblocks for the development of advanced chip-multiprocessors (CMPs). In this paper, we introduce a new angle to view transient thermal analysis - based on predicting thermal profile, instead of calculating it. We develop a systematic framework that can learn different thermal profiles of a CMP by using an autoregressive (AR) model. The proposed AR model can serve as a fast alternative for predicting the transient temperature of a CMP with reasonably good accuracy. Experimental results show that the proposed AR model can achieve approximately 113X speed-up over existing thermal profile estimation methods, while introducing an error of only 0.8°C on average.

A comprehensive and accurate latency model for Network-on-Chip performance analysis

In this work, we propose a new, accurate, and comprehensive analytical model for Network-on-Chip (NoC) performance analysis. Given the application communication graph, the NoC architecture, and the routing algorithm, the proposed framework analyzes the links dependency and then determines the ordering of queuing analysis for performance modeling. The channel waiting times in the links are estimated using a generalized G/G/1/K queuing model, which can tackle bursty traffic and dependent arrival times with general service time distributions. The proposed model is general and can be used to analyze various traffic scenarios for NoC platforms with arbitrary buffer and packet lengths. Experimental results on both synthetic and real applications demonstrate the accuracy and scalability of the newly proposed model.

SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model

In this work, we propose SVR-NoC, a learning-based support vector regression (SVR) model for evaluating Network-on-Chip (NoC) latency performance. Different from the state-of-the-art NoC analytical model, which uses classical queuing theory to directly compute the average channel waiting time, the proposed SVR-NoC model performs NoC latency analysis based on learning the typical training data. More specifically, we develop a systematic machine-learning framework that uses the kernel-based support vector regression method to predict the channel average waiting time and the traffic flow latency. Experimental results show that SVR-NoC can predict the average packet latency accurately while achieving about 120X speed-up over simulation-based evaluation methods.

Beyond Poisson: Modeling Inter-Arrival Time of Requests in a Datacenter

How frequently are computer jobs submitted to an industrial-scale datacenter? We investigate the trace that contains job requests and execution collected in one of large-scale industrial datacenters, which spans near half of a Terabyte. In this paper, we discover and explain two surprising patterns with respect to the inter-arrival time (IAT) of job requests: (a) multiple periodicities and (b) multi-level bundling effects. Specifically, we propose a novel generative process, Hierarchical Bundling Model (HiBM), for modeling the data. HiBM is able to mimic multiple components in the distribution of IAT, and to simulate job requests with the same statistical properties as in the real data. We also provide a systematic approach to estimate the parameters of HiBM.

Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations

Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits. This paper performs both the evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip-Multiprocessors (CMPs). Furthermore, this paper provides a learning-based model to predict the maximum temperature, based on which a simple, yet effective tier-stacking algorithm to mitigate the impact of variations on the temperature profile of 3D CMPs is proposed. Results show that (1) the proposed prediction model achieves more than 98% accuracy, (2) a 4-tier 3D implementation can be more than 40°C hotter than its 2D counterpart and (3) the proposed tier-stacking algorithm significantly improves the thermal yield from 44.4% to 81.1% for a 3D CMP.

Statistical thermal modeling and optimization considering leakage power variations

Unaddressed thermal issues can seriously hinder the development of reliable and low power systems. In this paper, we propose a statistical approach for analyzing thermal behavior under leakage power variations stemming from the manufacturing process. Based on the proposed models, we develop floorplanning techniques targeting thermal optimization. The experimental results show that peak temperature is reduced by up to 8.8°C, while thermal-induced leakage power and maximum thermal variance are reduced by 13% and 17%, respectively, with no additional area overhead compared with best performance-driven optimized design.

A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures

In this paper, we propose SVR-NoC, a network-onchip (NoC) latency model using support vector regression (SVR). More specifically, based on the application communication information and the NoC routing algorithm, the channel and source queue waiting times are first estimated using an analytical queuing model with two equivalent queues. To improve the prediction accuracy, the queuing theory-based delay estimations are included as features in the learning process. We then propose a learning framework that relies on SVR to collect training data and predict the traffic flow latency. The proposed learning methods can be used to analyze various traffic scenarios for the target NoC platform. Experimental results on both synthetic and real-application traffic demonstrate on average less than 12% prediction error in network saturation load, as well as more than 100× speedup compared to cycle-accurate simulations can be achieved.

Exploiting component dependency for accurate and efficient soft error analysis via Probabilistic Graphical Models

Abstract As the technology node continues to scale, soft errors have become a major issue for reliable processor designs. In this paper, we propose a framework that accurately and efficiently estimates the Architectural Vulnerability Factor (AVF) of critical storage structures of a processor. The proposed approach exploits the masking effects between array structure (e.g., register files and Caches) and logic units (e.g., Int-ALU) via the unified Probabilistic Graphical Models (PGM) methodology, and can provide guaranteed AVFs by two accuracy–efficiency tradeoff solutions. The experimental results have confirmed that, compared to current state-of-the-art approaches, the proposed framework achieves accurate and efficient estimation via two instanced solutions: (1) first-order masking effects up to 45.96% and on average 8.48% accuracy improvement with 52.01× speedup; (2) high-order masking effects average 87.28% accuracy improvement with 43.87× speedup. The two different accuracy–efficiency tradeoff of proposed MEA-PGM can be applied into different estimation scenarios (e.g., short time to market of general mobile devices and high reliable requirements in aerospace platforms) in flexibility.

A two-level approximate model driven framework for characterizing Multi-Cell Upsets impacts on processors

Abstract Soft error analysis is very significant for a good tradeoff between processor design cost (e.g. area and power) and reliability. In this paper, we propose an approximate model driven framework for efficient soft error analysis in processors. The proposed framework includes: 1) an approximate Probabilistic Graphical Model (PGM) for the Single Bit Upset (SBU) estimation, uses average-and-max policy to handle the mapped PGM structure, node parameter and inference fast; 2) an approximate boundary model for the more complex Multi-Cell Upsets (MCU) case, adopts relax-and-strict way to reuse the approximate PGM model and characterize MCU patterns completely. The comprehensive results confirm that, compared with the state-of-the-art, the proposed two-level methodology based on approximate models achieves fast estimation up to more 15.37× speedup while only 8.14% accuracy loss on average. Furthermore, the complex MCU impacts are also estimated by the proposed method at the same order of magnitude as the runtime of the simple SBU case.