Paul Bogdan

An Analytical Approach for Network-on-Chip Performance Analysis

Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we present a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

The Chip Is the Network: Toward a Science of Network-on-Chip Design

In this survey, we address the concept of network in three different contexts representing the deterministic, probabilistic, and statistical physics-inspired design paradigms. More precisely, we start by considering the natural representation of networks as graphs and discuss the main deterministic approaches to Network-on-Chip (NoC) design. Next, we introduce a probabilistic framework for network representation and optimization and present a few major approaches for NoC design proposed to date. Last but not least, we model the network as a thermodynamic system and discuss a statistical physics-based approach to characterize the network traffic. This formalism allows us to address the network concept in the most general context, point out the main limitations of the proposed solutions, and suggest a few open-ended problems.

Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip

As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for Systems-on-Chip (SoCs) are rapidly increasing. Relaxing the requirement of 100 % correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires SoCs to be designed with some degree of system-level fault-tolerance. Towards this end, this paper introduces a novel communication paradigm for SoCs, called stochastic communication. This scheme separates communication from computation by allowing the on-chip interconnect to be designed as a reusable IP and also provides a built-in tolerance to DSM failures, without a significant performance penalty. By using this communication scheme, a large percentage of data upsets, packet losses due to buffers overflow, and severe levels of synchronization failures can be tolerated, while providing high levels of performance.

Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design

Networks-on-chip (NoCs) have been proposed as a viable solution to solving the communication problem in multicore systems. In this new setup, mapping multiple applications on available computational resources leads to interaction and contention at various network resources. Consequently, taking into account the traffic characteristics becomes of crucial importance for performance analysis and optimization of the communication infrastructure, as well as proper resource management. Although queuing-based approaches have been traditionally used for performance analysis purposes, they cannot properly account for many of the traffic characteristics (e.g., non-stationarity, self-similarity) that are crucial for multicore platform design. To overcome these limitations, we propose a statistical physics inspired approach to capture the traffic dynamics in multicore systems. As shown later in this paper, this is of fundamental significance for re-thinking the very basis of multicore systems design; it also opens up new research directions into NoC optimization which require accurate models of time-dependent and space-dependent traffic behavior.

An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads

Reducing energy consumption in multi-processor systems-on-chip (MPSoCs) where communication happens via the network-on-chip (NoC) approach calls for multiple voltage/frequency island (VFI)-based designs. In turn, such multi-VFI architectures need efficient, robust, and accurate run-time control mechanisms that can exploit the workload characteristics in order to save power. Despite being tractable, the linear control models for power management cannot capture some important workload characteristics (e.g., fractality, non-stationarity) observed in heterogeneous NoCs, if ignored, such characteristics lead to inefficient communication and resources allocation, as well as high power dissipation in MPSoCs. To mitigate such limitations, we propose a new paradigm shift from power optimization based on linear models to control approaches based on fractal-state equations. As such, our approach is the first to propose a controller for fractal workloads with precise constraints on state and control variables and specific time bounds. Our results show that significant power savings (about 70%) can be achieved at run-time while running a variety of benchmark applications.

Statistical physics approaches for network-on-chip traffic characterization

In order to face the growing complexity of embedded applications, we aim to build highly efficient Network-on-Chip (NoC) architectures which can connect in a scalable manner various computational modules of the platform. For such networked platforms, it is increasingly important to accurately model the traffic characteristics as this is intimately related to our ability to determine the optimal buffer size at various routers in the network and thus provide analytical metrics for various power-performance trade-offs. In this paper, we show that the main limitations of queueing theory and Markov chain approaches to solving the buffer sizing problem can be overcome by adopting a statistical physics approach to probability density characterization which incorporates the power law distribution, correlations, and scaling properties exhibited within an NoC architecture due to various network transactions. As experimental results show, this new approach represents a breakthrough in accurate traffic modeling under non-equilibrium conditions. As such, our results can be directly used to solve the buffer sizing problem for multiprocessor systems where communication happens via the NoC approach.

Efficient Modeling and Simulation of Bacteria-Based Nanonetworks with BNSim

Bacteria-based networks are formed using native or engineered bacteria that communicate at nano-scale. This definition includes the micro-scale molecular transportation system which uses chemotactic bacteria for targeted cargo delivery, as well as genetic circuits for intercellular interactions like quorum sensing or light communication. To characterize the dynamics of bacterial networks accurately, we introduce BNSim, an open-source, parallel, stochastic, and multiscale modeling platform which integrates various simulation algorithms, together with genetic circuits and chemotactic pathway models in a complex 3D environment. Moreover, we show how this platform can be used to model synthetic bacterial consortia which implement a XOR function and aggregate nearby bacteria using light communication. Consequently, the results demonstrate how BNSim can predict various properties of realistic bacterial networks and provide guidance for their actual wet-lab implementations.

Towards a Science of Cyber-Physical Systems Design

Cyber-physical systems (CPS) represent the information technology quest of the 21-st century for a better, cleaner, safer life by integrating computation, communication, and control with physical processes. Physical processes are ubiquitously non-stationary and require time-dependent models for modeling and understanding their behavior. In contrast, most current computing platforms and their design methodologies lack proper models for the time component and mostly assume stationary (i.e., time independent) behavior. In this paper, we use empirical data to identify the main characteristics (e.g., self-similarity, nonstationarity) of various physical processes which can also be observed in the communication workload of real CPS. Starting from the complex characteristics of CPS workloads, we present a statistical physics inspired model which is used to define a new optimal control problem that not only accounts for the observed self-similarity and nonstationarity properties of the CPS workload, but also allows for accurate predictions on CPS dynamical trajectories during the optimization process.

QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors

This paper identifies non-stationary effects in grid like Network-on-Chip (NoC) traffic and proposes QuaLe, a novel statistical physics-inspired model, that can account for non-stationarity observed in packet arrival processes. Using a wide set of real application traces, we demonstrate the need for a multi-fractal approach and analyze various packet arrival properties accordingly. As a case study, we show the benefits of our multifractal approach in estimating the probability of missing deadlines in packet scheduling for chip multiprocessors (CMPs).

Workload characterization and its impact on multicore platform design

Networks-on-chip (NoCs) have been proposed as a scalable solution to solving the communication problem in multicore systems. Although the queuing-based approaches have been traditionally used for performance analysis purposes, they cannot properly account for many of the traffic characteristics (e.g., non-stationary, self-similarity, higher order statistics) that are crucial for multicore platform design when communication happens via the NoC approach. To overcome this limitation, we propose a mean field approach to analyze the traffic dynamics in multicore systems and show how the non-stationary effects of the NoC workload can be effectively captured; this is of fundamental significance for rethinking the very basis of multicore systems design. Moreover, our experimental results demonstrate that both network architecture and application characteristics are the main sources of power law behavior observed in network traffic. Our findings open new research directions into NoC optimization which require accurate models of time- and space-dependent traffic behavior.