Da-Jeong Yun

Improvements in the bending performance and bias stability of flexible InGaZnO thin film transistors and optimum barrier structures for plastic poly(ethylene naphthalate) substrates

Amorphous indium gallium zinc oxide thin-film transistors (TFTs) were fabricated and characterized on flexible poly(ethylene naphthalate) (PEN) substrates. A hybrid inorganic/organic double-layered barrier layer structure was proposed for enhancing the permeability and the surface roughness of the PEN substrates, which was composed of a 3 μm-thick spin-coated organic layer and a 50 nm-thick atomic-layer-deposited Al2O3 inorganic layer. The saturation mobility, subthreshold swing, and on/off ratio of the TFTs on the PEN substrates with the proposed hybrid barrier structure were found to be approximately 15.5 cm2 V−1 s−1, 0.2 V dec−1, and 2.2 × 108, respectively. These good TFT performances were not degraded even under the mechanical bending situation at a curvature radius of 3.3 mm and after the repetitive bending cycles. Furthermore, the variations in turn-on voltage of the TFT were evaluated to be approximately as small as −0.1 and +1.6 V under the negative and positive-bias stress tests, respectively.

High Performance and Stable Flexible Memory Thin-Film Transistors Using In–Ga–Zn–O Channel and ZnO Charge-Trap Layers on Poly(Ethylene Naphthalate) Substrate

A flexible charge-trap-type memory (f-CTM) thin-film transistor was proposed and fabricated on poly(ethylene naphthalate) (PEN) substrate. All the fabrication process temperature was suppressed below 180 °C. To improve the surface roughness and water vapor transmission rate of the PEN substrate, the organic/inorganic hybrid barrier layer was introduced. The gate-stack was composed of all oxide layers, such as In-Ga-Zn-O active channel, ZnO charge-trap layer, Al2O3 blocking/tunneling layers, and In-Sn-O transparent electrode, in which double-layered tunneling and top-protection layers were designed, so that the f-CTMs could exhibit stable and excellent device performance. As results, wide memory margin (25.6 V), fast programming speed (~500 ns), and long retention time (>3 h) were obtained at room temperature and at 80 °C. Furthermore, these memory device characteristics were not degraded even after the delamination of PEN substrate and under the bending situation with a given curvature radius (3.3 mm).

Process Optimization and Device Characterization of Nonvolatile Charge Trap Memory Transistors Using In–Ga–ZnO Thin Films as Both Charge Trap and Active Channel Layers

Charge-trap memory thin-film transistors (CTM-TFTs) using In-Ga-ZnO (IGZO) thin films as active channel and charge trap layers (CTLs) were fabricated and characterized. Technical strategies to optimize the device design parameters were categorized into the following three parts. At first, PO2 conditions during the sputtering deposition of IGZO CTL were varied to 1%, 2%, and 5% to modulate the electronic natures of the IGZO films. The device using the CTL deposited at PO2 of 1% obtained the largest memory window and exhibited the fastest program speed. Second, to investigate the thickness effects of double-layered tunneling oxide, the configuration was varied to 3/3 nm and 5/5 nm. From the viewpoints of process window, the 5/5 nm configuration was chosen for stable device characteristics. At last, the effects of CTL thickness, which affects the number of trap sites and carrier concentration of the film, was carefully investigated. A 30-nm-thick CTL showed most desirable behaviors, including superior memory operation and uniformity. The CTM-TFTs fabricated with optimum conditions exhibited the memory margin in programmed currents between ON-and OFF-states of 2.9 × 105 at 1-μs program voltage pulses with ±20 V. Furthermore, the ION/OFF of five-orders-of-magnitude was obtained even after the lapse retention time for 104 s.

Device characteristics comparisons for the InGaZnO thin film transistors fabricated on two-type surfaces of the plastic poly(ethylene naphthalate) substrates with hybrid barrier layers

The poly(ethylene naphthalate) (PEN) substrates have two sides of bare PEN and primer-coated surfaces treated to provide slip property for film production. Although the primer surface showed porous and inhomogeneous morphologies, a hybrid inorganic/organic double-layered barrier layer can effectively improve the surface roughness and permeability. The fabricated amorphous In-Ga-Zn-O thin-film transistors on the PEN substrates with hybrid barrier showed good performances and did not experience any degradation under the mechanical bending situation at a curvature radius of 3.3 mm. The variation in the threshold voltage was evaluated to be approximately −0.1/1.6 V under the negative/positive bias stress tests, respectively.

Areal Geometric Effects of a ZnO Charge-Trap Layer on Memory Transistor Operations for Embedded-Memory Circuit Applications

The areal geometric effects of a ZnO charge-trap layer (CTL) on the device characteristics of a charge-trap memory thin-film transistor were investigated for embedded-memory circuit applications. While the device with a larger overlapped region between the CTL and active channel exhibited a larger memory window and faster program speed, in order to guarantee long-term memory retention even under higher drain bias conditions, the CTL size should be minimized to reduce the overlapped area. The resulting device behavior is a compromise between the modulations of the number of trap sites within the ZnO CTL and the electric field concentration caused by the configuration of the edge area in the overlapped region.

Improvement in Sensing Responses to Ammonia Gas for Gas Sensors With Separately Designed Sensing Element Using ALD-Grown ZnO Nanoparticles and Read-Out Element of Top-Gate In-Ga-Zn-O Thin-Film Transistor

Ammonia (NH3) gas sensors with unique oxide semiconductor thin-film transistor (TFT) configuration using ZnO nanoparticles (NPs) as gas-sensing element were fabricated and their gas-sensing responses were evaluated. The ZnO NPs composing the sensing elements were synthesized using atomic layer deposition (ALD). The optimum ALD conditions for the particle-like island-growth of ZnO were established by systematically investigating the ALD temperature and cycle conditions from 140 °C to 160 °C and from 5 to 30, respectively. Controlled devices of the sensor TFTs were prepared with different ALD conditions, in which sensing and read-out elements were designed to be physically separated. This unique device configuration provided us both benefits of improvement in gas-sensing property and stability of the device characteristics. The device showed instant gas responses as well as stable device behaviors at different operating temperature even with repeated gas measurements. Sufficiently good response to NH3 were obtained at 150 °C, which was significantly lower than the operating temperature of previously reported NH3 gas sensors. Based on the results the combination of novel TFT configuration and ALD-prepared ZnO NPs could be an effective method for the improvement in device characteristics of the gas sensors.

Investigations on device design parameters of all-oxide transparent charge-trap memory thin-film transistors

Charge-trap memory thin film transistors employing In-Ga-Zn-O thin films as active channel and charge-trap layers (CTLs) were fabricated and characterized. To optimize process conditions, the design parameters were categorized into two parts. First, the thickness effects of double-layered tunneling oxide were examined and the 5 nm/5 nm configuration was chosen for guaranteeing process window and device performance. Secondly, the CTL thickness effects were investigated and the device using 30 nm-thick CTL showed most desirable behaviors including superior memory operation and device uniformity. The CTL geometry was also found to have significant impact on nonvolatile memory operations.