Da-Wen Lin
TSMC
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Publication
Featured researches published by Da-Wen Lin.
IEEE Electron Device Letters | 2007
Da-Wen Lin; Ming-Lung Cheng; Shyh-Wei Wang; Chung-Cheng Wu; Ming-Jer Chen
A new method of extracting the MOSFET series resistance is proposed. This method requires only simple dc measurements on a single test device. Experimental demonstration is presented, without requiring quantities such as gate-oxide thickness, physical gate length, or effective channel length. The merit of the method stems from the specifically arranged bias conditions in which the channel carrier mobility remains constant for high vertical electric fields. It is this unique property which makes the proposed method suitable for short-channel devices.
IEEE Transactions on Electron Devices | 2010
Da-Wen Lin; Ming-Lung Cheng; Shyh-Wei Wang; Chung-Cheng Wu; Ming-Jer Chen
A method of MOSFET series resistance extraction is established in this paper. The core of this method relies on the constant mobility criteria, while for different gate lengths, it preserves the shape of universal mobility curves in the high-vertical-field regime. Consequently, the series resistance of a MOSFET can be extracted in an analytical and self-consistent manner, achieved without the knowledge of the gate oxide thickness, channel length, channel doping, or channel stress. Reasonable values of extracted series resistance are demonstrated in a wide range of gate length. Technology computer-aided design simulation further corroborates the validity of the proposed method, particularly for devices with heavily doped source/drain extensions. The constant mobility criteria with respect to the bulk charge linearization coefficient are also verified.
IEEE Electron Device Letters | 2010
Da-Wen Lin; Chien-Liang Chen; Ming-Jer Chen; Chung-Cheng Wu
This letter proposes a novel process to modulate the distance, or proximity, between the tip of embedded silicon-germanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment is adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this letter, an extremely close proximity is achieved using self-aligned silicon reflow (SASR) in hydrogen ambient. As opposed to conventional approaches which have e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge, as corroborated by both the TEM analyses and TCAD simulation. A significant improvement in pMOSFET performance is also measured.
Archive | 2010
Ming-Lung Cheng; Yen-Chun Lin; Da-Wen Lin
Archive | 2010
Ming-Lung Cheng; Yen-Chun Lin; Da-Wen Lin
Archive | 2010
Chih-Hung Tseng; Da-Wen Lin; Chien-Tai Chan; Chia-Pin Lin; Li-Wen Weng; An-Shen Chang; Chung-Cheng Wu
Archive | 2013
Tung Ying Lee; Li-Wen Weng; Chien-Tai Chan; Da-Wen Lin; Hsien-Chin Lin
Archive | 2010
Da-Wen Lin; Che-Min Chu; Tsung-Hung Li; Chih-Hung Tseng; Yen-Chun Lin; Chung-Cheng Wu
Archive | 2015
King-Yuen Wong; Chia-Yu Lu; Chien-Chang Su; Yen-Chun Lin; Yi-Fang Pai; Da-Wen Lin
Archive | 2011
Ming-Lung Cheng; Yen-Chun Lin; Da-Wen Lin