Chung-Cheng Wu

Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25/spl deg/C to 125/spl deg/C) of the four components of off-state drain leakage (I/sub off/) (i.e. subthreshold leakage (I/sub sub/), gate edge-direct-tunneling leakage (I/sub EDT/), gate-induced drain-leakage (I/sub GIDL/), and bulk band-to-band-tunneling leakage (I/sub B-BTBT/)). In addition, the high temperature characteristics of I/sub off/ with reverse body bias (V/sub B/) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 /spl mu/m, 0.15 /spl mu/m, and 0.13 /spl mu/m). Experiments show that the optimum V/sub B/, which minimizes I/sub off/, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I/sub B-BTBT/ and I/sub GIDL/ by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I/sub G-on/) and I/sub EDT/ specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I/sub SB/) is also analyzed.

28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications

An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described.

On the SiO/sub 2/-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 /spl mu/m CMOS logic technology

This paper describes a leading-edge 0.13 /spl mu/m low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I/sub off/) and gate delay (T/sub d/) performance at operating voltages (V/sub cc/) of 1.5 V and 1.2 V, devices with 0.11 /spl mu/m nominal gate length (L/sub g-nom/) and various gate-oxide thicknesses (T/sub ox/) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 /spl Aring/ in order to keep acceptable off-state power consumption at V/sub cc/=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T/sub ox/=26 /spl Aring/) is targeted for V/sub cc/=1.5 V with worst case I/sub off/ <10 pA//spl mu/m and nominal gate delay 24 ps/gate. Another design, named LP1 (T/sub ox/=22 /spl Aring/) is targeted for V/sub cc/=1.2 V with worst case I/sub off/<20 pA//spl mu/m and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 /spl mu/A//spl mu/m nominal drive currents at V/sub cc/ for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 /spl mu/m/sup 2/ cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T/sub ox/=22 /spl Aring/) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125/spl deg/C and V/sub cc/=1.5 V.

A Millisecond-Anneal-Assisted Selective Fully Silicided (FUSI) Gate Process

We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (MSA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P+ FUSI gates for PMOSFETs while preserving a FUSI-free N+ poly-Si gate for NMOSFETs with the feature size down to 30 nm. A 20% improvement in FUSI- gated PMOSFET Ion- Ioff is measured, which can be attributed to the enhanced hole mobility and the elimination of P+ poly-gate depletion.

Device trends and implications on circuit design in advanced CMOS technologies

To conciliate scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization including dynamic body/well bias, gate dielectric scaling, mobility enhancement by strained-Si, SRAM process and design interactions, digital and analog device tradeoffs, and HV I/O considerations in advanced CMOS technologies.

Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.