Dae-Gyu Park

Robust ternary metal gate electrodes for dual gate CMOS devices

This report describes thermally stable dual metal gate electrodes for surface channel Si CMOS devices. We found that the ternary metal nitrides, i.e., Ti/sub 1-x/Al/sub x/N/sub y/ (TiAlN) and TaSi/sub x/N/sub y/ (TaSiN) films, are stable up to 1000/spl deg/C. Especially, the stoichiometric TiAlN (y/spl sim/1) exhibited highly robust p-type gate electrode (p-TiAlN) properties, demonstrating a work function (/spl Phi//sub m/) of /spl sim/5.1 eV and excellent gate oxide integrity against the thermal budget of conventional Si CMOS processing. The N-deficient TiAlN (y < 1) showed /spl Phi//sub m/ for n-type electrode (n-TiAlN) with limited thermal stability. The dual gate electrodes, p-TiAlN and TaSiN, exhibited negligible EOT (equivalent oxide thickness) variation on the high-k gate dielectrics (ZrO/sub 2/, HfO/sub 2/) up to 950/spl deg/C.

Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO2/Si metal–oxide–semiconductor structures

We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO2/p-Si metal–oxide–semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010u2009eV−1u200acm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process.

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal–oxide–semiconductor capacitors

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50–140u200aA)/SiO2(7u200aA)/p-Si metal–oxide–semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance–voltage hysteresis as small as ∼12 mV with the flatband voltage of −0.5 V and the interface trap density of ∼5×1010u200acm−2u200aeV−1 were attained with activation anneal at 750u200a°C. A high level of gate leakage current was observed at the activation temperatures over 750u200a°C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50u200aμm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800u200a°C anneal in N2 for 30 min.

Work function and thermal stability of Ti1−xAlxNy for dual metal gate electrodes

Work function and thermal stability of reactive sputtered Ti1−xAlxNy films were investigated for a metal gate electrode using a metal–oxide–semiconductor (MOS) structure. It is found that the work function (ΦM) values of Ti1−xAlxNy are ranged from 4.36 to 5.13 eV with a nitrogen partial flow rate (fN2). The ΦM values of Ti1−xAlxNy films, 4.36 eV for nMOS (n-Ti1−xAlxNy) and 5.10–5.13 eV for pMOS (p-Ti1−xAlxNy), may be applicable to dual metal gate electrodes. Excellent thermal stability up to 1000u200a°C was obtained on SiO2 as observed by the negligible change of capacitance equivalent thickness and Al 2p core level spectra for p-Ti1−xAlxNy (y∼1.0,fN2=50%), whereas a limited stability was attained in case of n-Ti1−xAlxNy (fN2⩽40%). The p-Ti1−xAlxNy can be a good candidate for pMOS device feasibility because of good thermal stability, while the n-Ti1−xAlxNy may be applicable for nMOS gate electrode in low thermal devices using damascene gate process.

Effects of TiN Deposition on the Characteristics of W / TiN / SiO2 / Si Metal Oxide Semiconductor Capacitors

We report the effects of the TiN deposition technique on the generation and annihilation of interface traps and oxide trapped charges in W/TiN/SiO 2 (2-6 nm)/Si metal oxide semiconductor (MOS) system during direct metal gate process. The TiN films were prepared by reactive sputtering using the Ti target or chemical vapor deposition (CVD) using TiCl 4 and NH 3 . Sputter-deposited TiN not only generated a high level of interface traps ∼2 X 10 12 eV -1 cm 2 from the bandedge to the near midgap of Si, hut also introduced oxide trapped charges (Q ol ) of ∼ 1 × 10 12 cm 2 . The damages annealed out for SiO 2 (≥3 nm) to the range of 2-3 X 10 11 eV -1 cm 2 by the post-metal anneal (PMA) at 800°C in N 2 or at 450°C in forming gas. The interfacial damages for ultrathin SiO 2 (∼ 2 nm), however, were hardly capable of relieving even after the PMA of 800°C, resulting in an interface trap density (D it ) in the high 10 11 eV -1 cm -2 range. The D it level created after CVD-TiN was as low as ∼3 × 10 11 eV -1 cm -2 with negligible Q ol even without PMA, and this level was further reduced to ∼1 X 10 11 eV -1 cm after PMA. We observed a noticeable increase of the capacitance equivalent thickness when prepared with CVD-TiN plausibly due to Cl from the source gas.

Boron penetration and thermal instability of p+ polycrystalline-Si/ZrO2/SiO2/n-Si metal-oxide-semiconductor structures

We report boron penetration and thermal instability of p+ polycrystalline-Si (poly-Si)/ZrO2 (100u2009A)/SiO2 (∼7 A)/n-Si metal-oxide-semiconductor (MOS) structures. The flatband voltage shift (ΔVFB) of the p+ poly-Si/ZrO2/SiO2/n-Si MOS capacitor as determined by capacitance–voltage measurement was ∼0.18 V, corresponding to a p-type dopant level of 1.1×1012 Bu2009ions/cm2 as the activation temperature increased from 800 to 850u2009°C. Additional ΔVFB of ∼0.24 V was measured after the anneal from 850 to 900u2009°C. Noticeable boron penetration into the n-type Si channel as observed by secondary ion mass spectroscopy also confirmed the VFB instability with activation annealing above 850u2009°C. An abnormal decrease of accumulation capacitance was also found after anneal at 900u2009°C due to an excessive leakage current which was attributed to the formation of ZrSix nodules at the poly-Si/ZrO2 interface. We observed 4–5 orders of magnitude lower leakage current from the small-size capacitors (<50×50 μm2) up to the activation anneal ...

Electrical and structural properties of nanolaminate (Al2O3/ZrO2/Al2O3) for metal oxide semiconductor gate dielectric applications

We investigated electrical and material properties of an untrathin nanolaminate (Al2O3/ZrO2/Al2O3) structure, prepared by atomic-layer chemical vapor deposition (ALCVD), for use in metal-oxide-semiconductor gate dielectric applications. The properties of nanolaminate were characterized by various technique such as high-resolution transmission electron microscopy (HRTEM), medium-energy ion scattering (MEIS), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and electrical analysis of MOS capacitors. Compared with the roughness of ZrO2 on bare silicon, ZrO2 on Al2O3 shows negligible roughness confirmed by AFM and HRTEM. Excellent electrical characteristics such as an equivalent oxide thickness (EOT) of 10.2 A and a leakage current density of 3×10-4 A/cm2 were obtained at 1 V below the flatband voltage. The conduction mechanism of nanolaminate can be explained by trap-assisted tunneling through ZrO2 and direct tunneling through Al2O3.

Suppressed boron penetration in p+ polycrystalline-Si/Al2O3/Si metal–oxide–semiconductor structures

We demonstrate a suppressed boron penetration in p+ polycrystalline-Si (poly-Si)/Al2O3/n-Si metal–oxide–semiconductor (MOS) capacitors using a remote plasma nitridation (RPN) of Al2O3 surface. The B penetration was sufficiently suppressed for temperature to 850u200a°C in N2 for 30 min as manifested by the negligible flat band shift (ΔVFB) and insignificant B diffusion. The nitrogen (N) incorporation in Al2O3 surface appears to effectively impede the B diffusion into the Si channel. Increased gate leakage current for the n+ poly-Si/RPN-Al2O3/p-Si n-type MOS capacitors was observed and attributed to the reduced band gap energy of RPN-Al2O3 due to the formation of AlN and bulk defects due to RPN. Optimization of N concentration is required for the suppressed B penetration and leakage reduction.

Epitaxial C49–TiSi2 phase formation on the silicon (100)

The crystallographic characteristics of an epitaxial C49–TiSi2 island formed on the Si (100) substrate were investigated by high-resolution transmission electron microscopy (HRTEM). The analysis results clearly showed that the optimum epitaxial relationship between the C49–TiSi2 phase and the Si substrate is [001]C49//[011]Si and (010)C49//(100)Si. We found that the interfacial energy at the C49–TiSi2/Si interface is relaxed by the formation of misfit dislocations and/or atomic steps, and consequently the epitaxial C49 phase is thermally stable so it is not transformed to the C54 phase even after high-temperature annealing above 900u200a°C. Further, the mechanism on the formation of the epitaxial C49 phase on the Si substrate and the atomic arrangement of stacking faults lying on the C49 (020) plane are discussed through the analysis of HRTEM images.

Reliability Characteristics of W / WN / TaO x N y / SiO2 / Si Metal Oxide Semiconductor Capacitors

We investigated the effects of post-gate anneal and WN sputtering power on the gate dielectric integrity of W/WN/TaO x N y /SiO 2 /Si metal oxide semiconductor (MOS) capacitors. The process damage induced by physical vapor deposited metal gates in the high-permittivity (k) gate dielectric was partially relieved by a post-gate anneal. This is manifested by reduced leakage current, higher wear-out breakdown voltage, reduced charge trapping, and improved interface characteristics such as reduced hysteresis and interface state density (D it ). We observed a noticeable increase of charge trapping and interfacial roughness at the WN/TaO x N y interface with WN power density while the D it level remained similar. Degradation in the reliability characteristics with sputtering power density might be attributed to irrecoverable damage in the TaO x N y film.