Kwan-Yong Lim

Characteristics of n+ polycrystalline-Si/Al2O3/Si metal–oxide– semiconductor structures prepared by atomic layer chemical vapor deposition using Al(CH3)3 and H2O vapor

We report interface and dielectric reliability characteristics of n+ polycrystalline-silicon (poly-Si)/Al2O3/Si metal–oxide–semiconductor (MOS) capacitors. Al2O3 films were prepared by atomic layer chemical vapor deposition using Al(CH3)3 and H2O vapor. Interface state density (Dit) and dielectric reliability properties of n+ poly-Si/Al2O3/Si MOS structures were examined by capacitance–voltage, conductance, current–voltage, and time-dependent dielectric breakdown measurements. The Dit of the n+ poly-Si/Al2O3/Si MOS system near the Si midgap is approximately 8×1010 eV−1 cm−2 as determined by the conductance method. Frequency dispersion as small as ∼20 mV and hysteresis of ∼15 mV were attained under the electric field of ±8 MV/cm. The gate leakage current of ∼36 A effective thickness Al2O3 dielectric measured at the gate voltage of −2.5 V is ∼−5 nA/cm2, which is approximately three orders of magnitude lower than that of a controlled oxide (SiO2). Time-dependent dielectric breakdown data of Al2O3/Si MOS capa...

Robust ternary metal gate electrodes for dual gate CMOS devices

This report describes thermally stable dual metal gate electrodes for surface channel Si CMOS devices. We found that the ternary metal nitrides, i.e., Ti/sub 1-x/Al/sub x/N/sub y/ (TiAlN) and TaSi/sub x/N/sub y/ (TaSiN) films, are stable up to 1000/spl deg/C. Especially, the stoichiometric TiAlN (y/spl sim/1) exhibited highly robust p-type gate electrode (p-TiAlN) properties, demonstrating a work function (/spl Phi//sub m/) of /spl sim/5.1 eV and excellent gate oxide integrity against the thermal budget of conventional Si CMOS processing. The N-deficient TiAlN (y < 1) showed /spl Phi//sub m/ for n-type electrode (n-TiAlN) with limited thermal stability. The dual gate electrodes, p-TiAlN and TaSiN, exhibited negligible EOT (equivalent oxide thickness) variation on the high-k gate dielectrics (ZrO/sub 2/, HfO/sub 2/) up to 950/spl deg/C.

Lateral wet oxidation of AlxGa1−xAs‐GaAs depending on its structures

Data are presented demonstrating that the lateral wet oxidation of Al(Ga)As layer is strongly influenced by its thicknesses and heterointerface structures as well as Al compositions. The oxidation length decreases rapidly with decreasing AlAs thickness in the range of <80 nm and oxidation nearly stops at a thickness of ∼11 nm. Also, the oxidation rate of AlxGa1−xAs decreases quickly with decreasing Al composition, providing a high degree of oxidation selectivity. AlGaAs layers on both sides of AlAs layer reduce the lateral oxidation rate which is enhanced by the stress induced by oxidized AlAs.

Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO2/Si metal–oxide–semiconductor structures

We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO2/p-Si metal–oxide–semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010 eV−1 cm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process.

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal–oxide–semiconductor capacitors

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50–140 A)/SiO2(7 A)/p-Si metal–oxide–semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance–voltage hysteresis as small as ∼12 mV with the flatband voltage of −0.5 V and the interface trap density of ∼5×1010 cm−2 eV−1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Novel damage-free direct metal gate process using atomic layer deposition

We report the impact of atomic layer deposition (ALD)-TiN on the novel characteristics of the W/TiN/SiO/sub 2//p-Si MOS system. A damage-free direct metal gate was attained using ALD-TiN as manifested by the negligible hysteresis and low interface trap density (D/sub it/) of /spl sim/5/spl times/10/sup 10/ eV/sup -1/cm/sup -2/ near the Si midgap. Gate leakage current level gated with ALD-TiN is remarkably lower than that with physical vapor deposition (PVD)-TiN or poly-Si gate at a similar capacitance equivalent thickness (CET). In addition, ALD-TiN demonstrated highly robust gate oxide reliability with negligible CET variation against high thermal budget, paving the way for the direct metal gate process.

Hole transport in Mg-doped GaN epilayers grown by metalorganic chemical vapor deposition

A two-band model involving the heavy- and light-hole bands was adopted to analyze the temperature-dependent Hall effect measured on Mg-doped p-type GaN epilayers. At 300 K, the hole concentration was determined to be nearly twice the Hall concentration estimated from the measured Hall coefficient, meanwhile the Hall mobility of heavy hole turned out to be only half of the measured one. It is shown that the scattering by space charge and acoustic deformation potential is anomalously enhanced in Mg-doped GaN, and that the light hole affects conspicuously the observed transport parameters.

Effects of TiN Deposition on the Characteristics of W / TiN / SiO2 / Si Metal Oxide Semiconductor Capacitors

We report the effects of the TiN deposition technique on the generation and annihilation of interface traps and oxide trapped charges in W/TiN/SiO 2 (2-6 nm)/Si metal oxide semiconductor (MOS) system during direct metal gate process. The TiN films were prepared by reactive sputtering using the Ti target or chemical vapor deposition (CVD) using TiCl 4 and NH 3 . Sputter-deposited TiN not only generated a high level of interface traps ∼2 X 10 12 eV -1 cm 2 from the bandedge to the near midgap of Si, hut also introduced oxide trapped charges (Q ol ) of ∼ 1 × 10 12 cm 2 . The damages annealed out for SiO 2 (≥3 nm) to the range of 2-3 X 10 11 eV -1 cm 2 by the post-metal anneal (PMA) at 800°C in N 2 or at 450°C in forming gas. The interfacial damages for ultrathin SiO 2 (∼ 2 nm), however, were hardly capable of relieving even after the PMA of 800°C, resulting in an interface trap density (D it ) in the high 10 11 eV -1 cm -2 range. The D it level created after CVD-TiN was as low as ∼3 × 10 11 eV -1 cm -2 with negligible Q ol even without PMA, and this level was further reduced to ∼1 X 10 11 eV -1 cm after PMA. We observed a noticeable increase of the capacitance equivalent thickness when prepared with CVD-TiN plausibly due to Cl from the source gas.

Boron penetration and thermal instability of p+ polycrystalline-Si/ZrO2/SiO2/n-Si metal-oxide-semiconductor structures

We report boron penetration and thermal instability of p+ polycrystalline-Si (poly-Si)/ZrO2 (100 A)/SiO2 (∼7 A)/n-Si metal-oxide-semiconductor (MOS) structures. The flatband voltage shift (ΔVFB) of the p+ poly-Si/ZrO2/SiO2/n-Si MOS capacitor as determined by capacitance–voltage measurement was ∼0.18 V, corresponding to a p-type dopant level of 1.1×1012 B ions/cm2 as the activation temperature increased from 800 to 850 °C. Additional ΔVFB of ∼0.24 V was measured after the anneal from 850 to 900 °C. Noticeable boron penetration into the n-type Si channel as observed by secondary ion mass spectroscopy also confirmed the VFB instability with activation annealing above 850 °C. An abnormal decrease of accumulation capacitance was also found after anneal at 900 °C due to an excessive leakage current which was attributed to the formation of ZrSix nodules at the poly-Si/ZrO2 interface. We observed 4–5 orders of magnitude lower leakage current from the small-size capacitors (<50×50 μm2) up to the activation anneal ...

Thermal Stability of TaSi x N y Films Deposited by Reactive Sputtering on SiO2

The thermal stability of TaSi x N y /SiO 2 /p-type Si metal-insulator-semiconductor structure has been evaluated by measuring equivalent oxide thickness (EOT) from capacitance-voltage curves and gate leakage current as a function of annealing temperatures. TaSi x N y films were deposited using reactive sputtering from a TaSi 2 target, varying the nitrogen/argon flow ratio. A reaction between Ta 53 Si 47 and SiO 2 was observed after a 1000°C anneal, resulting in the increase of interfacial roughness and oxide thickness in the TaSi x N y /SiO 2 /p-Si structures. Cross-sectional transmission electron microscopy shows no indication of an interfacial reaction or crystallization in Ta 22 Si 29 N 49 on SiO 2 up to 1000°C as manifested by the negligible change in EOT and the stable leakage currents density (2.0 x 10 -6 A/cm 2 at V g = -1 V). The presence of Si-N bonds is attributed to cause the amorphous nature of the high N-containing TaSi x N y films. This may retard the formation of an interface layer and improve the chemical-thermal stability of the gate electrode/dielectric interface and oxygen diffusion barrier properties under high-temperature annealing.