Dae-Myeong Geum

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

In 0.53 Ga 0.47 As-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Utilizing Y 2 O 3 Buried Oxide

In this letter, we have investigated electrical properties of metal-oxide-semiconductor (MOS) gate stack of Pt/Y₂O₃/In_0.53Ga_0.47As under different annealing conditions. We have found that proper annealing step significantly improves MOS interfacial properties of Pt/Y₂O₃/In_0.53Ga_0.47As MOS capacitors. Finally, we have realized MOS interface with a low density of trap state (D_it) of 4 × 1012 eV^-1 · cm^-2 and hysteresis of 15 mV using postmetallization annealing at 350°C. Furthermore, we also first demonstrated In_0.53Ga_0.47As-on-insulator (-OI) transistors with Y₂O₃ buried oxide layer using developed MOS interface. Fabricated In_0.53Ga_0.47As-OI transistors show good I-V characteristics and high peak mobility of ~2000 cm²/Vs.

Fabrication of high-quality GaAs-based photodetector arrays on Si

We report on fabrication and characterization of high-quality 32 × 32 GaAs photodetector (PD) arrays on Si substrates fabricated by wafer bonding and epitaxial lift-off (ELO) techniques. Fabricated GaAs PD arrays showed good crystal quality on Si substrates with Raman spectra and X-ray diffraction measurement. Also, pitch scaling gave us faster ELO process time as well as high-density PD arrays. Furthermore, we investigated electrical and optical characteristics of fabricated GaAs pin PD arrays on Si substrates. Especially, the components of dark current characteristics were also evaluated, because it is very important to explore further pitch scaling.

InGaP/GaAs heterojunction phototransistors transferred to a Si substrate by metal wafer bonding combined with epitaxial lift-off.

We report fabrication and optical characteristics of an InGaP/GaAs heterojunction phototransistor (HPT) transferred to a Si substrate by a metal wafer bonding (MWB) and epitaxial lift-off (ELO) process at room temperature. An intermediate Pt/Au double layer between the HPT layer and Si provided a very smooth surface by which to achieve the MWB, and excellent durability against the acid solution during the ELO process. These processes were observed using scanning electron microscope (SEM) and atomic force microscopy (AFM). While the results on a low temperature photoluminescence (LTPL) signal and high resolution x-ray diffraction (HRXRD) rocking curve of the bonded device film implied a defect-free bonding, a very low collector dark current of the fabricated HPT was observed. The optical performance of a bonded InGaP/GaAs HPT on Si, operating at 635 nm wavelength is also investigated.

Fabrication of InGaAs-on-Insulator Substrates Using Direct Wafer-Bonding and Epitaxial Lift-Off Techniques

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III–V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. This method provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OI metal-oxide-semiconductor field-effect-transistors fabricated through the proposed DWB and ELO.

High hole mobility in strained In0.25Ga0.75Sb quantum well with high quality Al0.95Ga0.05Sb buffer layer

We have demonstrated high hole mobility in strained In0.25Ga0.75Sb quantum well (QW) structure with a high quality Al0.95Ga0.05Sb buffer layer for future single channel complementary metal-oxide-semiconductor circuits. The Al0.95Ga0.05Sb buffer layer is important to achieve low substrate leakage and guarantee good channel material quality and high hole mobility. We grew buffer layers with various Sb effective flux conditions using molecular beam epitaxy to obtain high crystal quality and proper electrical properties. We systematically evaluated the relationship between the crystal quality and electrical properties using X-ray diffraction, atomic force microscope, Raman, and the Hall effect measurement system. Then, on this optimized buffer layer, we grew the In0.2Al0.8Sb/In0.25Ga0.75Sb/linear-graded Al0.8Ga0.2Sb QW structure to obtain high hole mobility with compressive strain. Moreover, the compressive strain and hole mobility were measured by Raman and Hall effect measurement system. The results show a compressive strain value of 1.1% in In0.25Ga0.75Sb QW channel, which is very close to the theoretical value of 1.1% from lattice mismatch, exhibiting the highest hole mobility of 1170 cm2/V s among reported mobility in In0.25Ga0.75Sb QW. Furthermore, it was able to be fabricated as p-type Fin-FET and shown the excellent electrical characteristics with low Smin and high gm.We have demonstrated high hole mobility in strained In0.25Ga0.75Sb quantum well (QW) structure with a high quality Al0.95Ga0.05Sb buffer layer for future single channel complementary metal-oxide-semiconductor circuits. The Al0.95Ga0.05Sb buffer layer is important to achieve low substrate leakage and guarantee good channel material quality and high hole mobility. We grew buffer layers with various Sb effective flux conditions using molecular beam epitaxy to obtain high crystal quality and proper electrical properties. We systematically evaluated the relationship between the crystal quality and electrical properties using X-ray diffraction, atomic force microscope, Raman, and the Hall effect measurement system. Then, on this optimized buffer layer, we grew the In0.2Al0.8Sb/In0.25Ga0.75Sb/linear-graded Al0.8Ga0.2Sb QW structure to obtain high hole mobility with compressive strain. Moreover, the compressive strain and hole mobility were measured by Raman and Hall effect measurement system. The results show a ...

Fabrication and characterization of Pt/Al2O3/Y2O3/In0.53Ga0.47As MOSFETs with low interface trap density

In this work, we fabricated the In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a MOS interface of Y2O3/In0.53Ga0.47As and recessed gate structure. We investigated the interfacial properties of the gate stack and the junction characteristics of the fabricated MOSFETs. Low subthreshold slope (SS = 110 mV/dec), high on/off current ratio (Ion/Ioff = 106), and high effective mobility of 1600 cm2/V·s were achieved in the MOSFETs at a sheet charge density (Ns) = 1.2 × 1012 cm−2. From the temperature dependence of I–V characteristics, the interface trap density was extracted to be Dit = 2.2 × 1011 cm−2·eV−1 with a negligible trap-assisted leakage current.

Cost-effective fabrication of In 0.53 Ga 0.47 As-on-insulator on Si for monolithic 3D via novel epitaxial lift-off (ELO) and donor wafer re-use

Defect-less semiconductor-on-insulator (-OI) by a cost-effective and low temperature process is strongly needed for monolithic 3D (M3D) integration. Toward this, in this paper, we present a cost-effective fabrication of the InGaAs-OI structure featuring the direct wafer bonding (DWB) and the epitaxial lift-off (ELO) techniques as well as the re-use of the InP donor wafer. We systematically investigated the effects of the pre-patterning of the III-V layer before DWB, surface reforming (hydrophilic), and electro-chemical etching to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. We also demonstrated the re-usability of the InP donor wafer. Finally, as a result of the high film quality of the InGaAs channel combined with DWB and ELO, fabricated InGaAs-OI MOSFETs show a record-high effective mobility of ∼2800 cm2/Vs among surface channel Ino.53Gao.47As MOSFETs reported so far.

High-speed epitaxial lift-off for III-V-on-insulator transistors on Si substrates

Thin body III-V-on-insulator (III-V-OI) structure is a promising device structure for future node transistors in CMOS technology. Typically, a direct wafer bonding (DWB) is used to fabricate III-V-OI on a Si substrate [1-3]. Donor wafers were etched out [1, 2] or separated by hydrogen implantation [3]. However, the former one is extremely costly and the latter one can induce the residual defects in the channel layer. Therefore, a cost-effective and non-destructive technology to fabricate III-V-OI becomes more important. On the other hand, an epitaxial lift-off (ELO), which splits donor wafer and device active layer by selective etching of sacrificial layer located between the two, is quite promising to meet the two requirements of low cost and defect issue [5]. However, conventional ELO needs a long processing time to etch thin sacrificial layer across the whole wafer as shown in Fig. 1. In this work, we developed high-speed ELO techniques via pre-patterning and surface hydrophilization and fabricated conceptual devices of GaAs-OI transistors.

Low-Subthreshold-Slope Asymmetric Double-Gate GaAs-on-Insulator Field-Effect-Transistors on Si

In this letter, we have demonstrated low-subthreshold-slope (SS) asymmetric double-gate (DG) GaAs-on-insulator field-effect-transistors (FETs) on Si substrates via wafer bonding and epitaxial liftoff techniques. We found that DG FETs show lower SS than single-gate FETs all over the range of the drain current. A minimum value of SS was 68 mV/decade, which is very close to the theoretical limit. In addition, the achieved SS value was a record-low among the reported GaAs transistors so far.