Seong Kwang Kim

Modeling and Characterization of the Abnormal Hump in n-Channel Amorphous-InGaZnO Thin-Film Transistors After High Positive Bias Stress

Hump characteristics of n-channel amorphous indium-gallium-zinc-oxide (a-InGaZnO) thin-film transistors (TFTs) after positive gate and drain bias stress (PGDBS) are investigated. With the increase of the PGDBS time, we observed not only a shift of the threshold voltage (V_T) but also a generation of the hump in the transfer characteristics. The hump is caused by the localized trapping of electrons in the gate insulator over the gate-source overlap region by the high vertical field during the PGDBS (V_GS = 30, V_DS = 30; V_GD = V_GS - V_DS = 0 V). The TFT with a hump after PGDBS is modeled as a series connection of main and parasitic TFTs. The parasitic TFT for the electron trapping at the gate-source overlap region has a higher threshold voltage (V_Tp) and a shorter effective channel length (L_chp ≅ Lov) compared with those (V_Tm and L_ch) of the main TFT.

Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET

Separate extraction of source (RS) from drain resistance (RD) is important in the systematic modeling of electrical characteristics and investigation of physical mechanism related to the performance and reliability in MOSFETs and their integrated circuits. We report a hybrid open drain method (ODM), as a fully current-based characterization technique, for a comprehensive separation of asymmetric source and drain resistance components in a single MOSFET. In the hybrid ODM, the ODM through the parasitic bipolar transistor is combined with the dual-sweep combinational transconductance technique, the channel resistance method, and the parasitic junction current method. We fully considered the asymmetry in the source and the drain possibly caused by the layout, process, and degradation under bias. We successfully extracted the resistance components with RSe = 6.66-7.35 Q, RDe = 7.64-8.34 Q, RSo = 0.78-8.07 Q, RDo = 1.11-10.08 Q, and RSUB = 6.29-9.17 Q in the n-channel MOSFETs. RSe (RDe) is the VGS-independent external source (drain) resistance. RSo (RDo) is the VGS-independent external spreading source (drain) resistance and RSi (RDi) is the VGS-dependent intrinsic source (drain) resistance, respectively. RSUB is the substrate resistance. The hybrid ODM is expected to be useful in the characterization of parasitic resistances in each MOSFET with asymmetry caused by the layout, process, and degradation without using multiple devices with different channel length (L) and width (W) for measurement.

Fabrication of InGaAs-on-Insulator Substrates Using Direct Wafer-Bonding and Epitaxial Lift-Off Techniques

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III–V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. This method provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OI metal-oxide-semiconductor field-effect-transistors fabricated through the proposed DWB and ELO.

Comprehensive separate extraction of parasitic resistances in MOSFETs considering the gate bias-dependence and the asymmetric overlap length

Abstract Parasitic resistances cause degradation of transconductance (gm), cutoff frequency (fT), current driving capability, and long term reliability of MOSFETs. We report a comprehensive extraction of parasitic resistance components in MOSFETs for the contact, the spreading current path, and the lightly doped drain region caused by the process, structure, and degradation. We considered the gate bias (VGS)-dependence and the asymmetric overlap length (Lov,SD) in the source and drain. We report systematically integrated extraction technique combined with the channel resistance method, the transfer length method, the dual-sweep combinational transconductance technique, the open drain method, and the parasitic junction current method. VGS-independent resistances were separated to be RSe = 6.8–6.9 Ω, RDe = 7.4–7.5 Ω, RSUB = 7.4–7.6 Ω, RSo = 1.8–2.1 Ω, and RDo = 3.2–3.5 Ω for MOSFETs with and at W/L = 50 μm/0.27 μm. VGS-dependent intrinsic resistances are obtained to be RSi = 1.9–4.4 Ω, RDi = 1.4–3.2 Ω for the same devices. The VGS-dependent intrinsic channel resistance (RCH) is extracted with different channel lengths for MOSFETs with L = 0.18 μm/0.27 μm/0.36 μm.

Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si

We demonstrated ultra-thin-body (UTB) junctionless (JL) p-type field-effect transistors (pFETs) on Si using GaAs channels. Wafer bonding and epitaxial lift-off techniques were employed to fabricate the UTB p-GaAs-on-insulator on a Si template. Subsequently, we evaluated the JL FETs having different p-GaAs channel thicknesses considering both maximum depletion width and doping concentration for high performance. Furthermore, by introducing a double-gate operation, we more effectively controlled threshold voltage and attained an even higher ION/IOFF of >106, as well as a low subthreshold swing value of 300 mV/dec.

Fabrication and characterization of Pt/Al2O3/Y2O3/In0.53Ga0.47As MOSFETs with low interface trap density

In this work, we fabricated the In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a MOS interface of Y2O3/In0.53Ga0.47As and recessed gate structure. We investigated the interfacial properties of the gate stack and the junction characteristics of the fabricated MOSFETs. Low subthreshold slope (SS = 110 mV/dec), high on/off current ratio (Ion/Ioff = 106), and high effective mobility of 1600 cm2/V·s were achieved in the MOSFETs at a sheet charge density (Ns) = 1.2 × 1012 cm−2. From the temperature dependence of I–V characteristics, the interface trap density was extracted to be Dit = 2.2 × 1011 cm−2·eV−1 with a negligible trap-assisted leakage current.

Cost-effective fabrication of In 0.53 Ga 0.47 As-on-insulator on Si for monolithic 3D via novel epitaxial lift-off (ELO) and donor wafer re-use

Defect-less semiconductor-on-insulator (-OI) by a cost-effective and low temperature process is strongly needed for monolithic 3D (M3D) integration. Toward this, in this paper, we present a cost-effective fabrication of the InGaAs-OI structure featuring the direct wafer bonding (DWB) and the epitaxial lift-off (ELO) techniques as well as the re-use of the InP donor wafer. We systematically investigated the effects of the pre-patterning of the III-V layer before DWB, surface reforming (hydrophilic), and electro-chemical etching to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. We also demonstrated the re-usability of the InP donor wafer. Finally, as a result of the high film quality of the InGaAs channel combined with DWB and ELO, fabricated InGaAs-OI MOSFETs show a record-high effective mobility of ∼2800 cm2/Vs among surface channel Ino.53Gao.47As MOSFETs reported so far.

High-speed epitaxial lift-off for III-V-on-insulator transistors on Si substrates

Thin body III-V-on-insulator (III-V-OI) structure is a promising device structure for future node transistors in CMOS technology. Typically, a direct wafer bonding (DWB) is used to fabricate III-V-OI on a Si substrate [1-3]. Donor wafers were etched out [1, 2] or separated by hydrogen implantation [3]. However, the former one is extremely costly and the latter one can induce the residual defects in the channel layer. Therefore, a cost-effective and non-destructive technology to fabricate III-V-OI becomes more important. On the other hand, an epitaxial lift-off (ELO), which splits donor wafer and device active layer by selective etching of sacrificial layer located between the two, is quite promising to meet the two requirements of low cost and defect issue [5]. However, conventional ELO needs a long processing time to etch thin sacrificial layer across the whole wafer as shown in Fig. 1. In this work, we developed high-speed ELO techniques via pre-patterning and surface hydrophilization and fabricated conceptual devices of GaAs-OI transistors.

Low-Subthreshold-Slope Asymmetric Double-Gate GaAs-on-Insulator Field-Effect-Transistors on Si

In this letter, we have demonstrated low-subthreshold-slope (SS) asymmetric double-gate (DG) GaAs-on-insulator field-effect-transistors (FETs) on Si substrates via wafer bonding and epitaxial liftoff techniques. We found that DG FETs show lower SS than single-gate FETs all over the range of the drain current. A minimum value of SS was 68 mV/decade, which is very close to the theoretical limit. In addition, the achieved SS value was a record-low among the reported GaAs transistors so far.