Daekyu Yu

A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.

A Highly Efficient and Linear Class-AB/F Power Amplifier for Multimode Operation

The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems.

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.

A Ultra-High PAE Doherty Amplifier Basedon 0.13-

A 2.4-GHz Doherty CMOS power amplifier (PA) with ultra-high efficiency [power added efficiency (PAE)] is presented. A 0.13-mum standard CMOS process is employed and the two-stage circuit is configured for a 3.2-V operation. For a compact realization of the circuit, all matching circuits including a quarter wave transformer and input phase compensation transmission lines are implemented with lumped components. To modulate properly and maximize the PAE at P1 dB, the input power of the class C peaking power cell is adjusted by optimizing the gate bias of the peaking driver cell. By doing so, the gain compression of the carrier cell is compensated by the gain expansion of the peaking cell up to the full power. This amplifier delivers a 22.7dBm of P1 dB and 60% of PAE with 25dB of power gain at 2.4 GHz. The PAE at 5 dB backed-off power level shows about 35%. The excellent PAE of the circuit is the best data ever reported from linear CMOS PAs. The successful demonstration of the Doherty CMOS PA with lumped components is expected to be applied for a full-integration of the circuit

mu

Fully integrated Doherty amplifiers have been developed for 5 GHz wireless-LAN (WLAN) applications. Through a new Doherty power amplifier circuit topology, the bulky Doherty in/output matching block including quarter-wave (lambda/4) impedance transformer can be fully integrated using capacitors, short micro-strip lines and bonding wires. To improve efficiency at a full power, without using the bulky input power splitter, a new input power driving concept is implemented by inserting lambda/4 impedance transformers at the inputs of the carrier and peaking amplifiers using the lumped elements. The amplifier based on InGaP HBT technology, shows an output power of 22.5 dBm and a power-added efficiency (PAE) of 21.3 % at an error vector magnitude (EVM) of 5%, measured with 54 Mbps 64-QAM-OFDM signals at 5.2 GHz. The proposed in/output matching topology allows the fully integrated Doherty amplifiers with a small size

m CMOS Process

The Doherty power amplifier for mobile WiMAX application is fully integrated in 1.2×1.2 mm2 using a 2-µm InGaP/GaAs HBT process. The direct input power dividing technique is employed on a chip. Broadband input and output matching techniques are used for broadband Doherty operation. A 1.5 times larger peaking amplifier than carrier amplifier is used to have high efficiency for IEEE 802.16e m-WiMAX signal, which has 9.6 dB crest factor and 8.75 MHz bandwidth. The PA with a supply voltage of 3.4V has an EVM of 2.3% and a PAE of 31.5% at an output power of 24.75 dBm and an operating frequency of 2.6 GHz. The PAE of over 30.3% and the output power of over 24.6 dBm with the EVM of lower than 3.15% and the gain variation of 0.2 dB are achieved across 2.5∼2.7 GHz without any assistant technique for linearization.

Fully integrated Doherty power amplifiers for 5 GHz wireless-LANs

The input power drive of Doherty power amplifier (PA) is analyzed and a proper input dividing technique without a coupler is introduced. The efficiency and linearity are enhanced by the uneven power drive and proposed output matching circuits. The PA circuit is realized using a 2-µm InGaP/GaAs HBT process and combined using merged lumped-components for Doherty operation. For wireless broadband (WiBro) application, which has 9.54 dB crest factor and 8.75 MHz bandwidth, the PA has EVM of 3% and PAE of 40.2% at an output power of 26 dBm. This data represents that the PA has an excellent efficiency and linearity performance for handset applications, while eliminating the burden of a coupler.

30.3% PAE HBT Doherty power amplifier for 2.5∼2.7 GHz mobile WiMAX

InP-based single heterojunction bipolar transistors (SHBTs) for high-speed circuit applications were developed. Typical common emitter DC current gain (/spl beta/) and BV/sub CEO/ were about 17 and 10 V, respectively. Maximum extrapolated f/sub max/ of 478 GHz with f/sub T/ of 154 GHz was achieved for 0.5 /spl times/ 10 /spl mu/m/sup 2/ emitter size devices at 300 kA/cm/sup 2/ collector current density and 1.5 V collector bias. This is the highest f/sub max/ ever reported for any nontransferred substrate HBTs, as far as the authors know. This paper highlights the optimized conventional process, and the authors have great hopes for the process that offers inherent advantages for the direct implementation to high-speed electronic circuit fabrication.

Input power dividing of Doherty power amplifiers for handset applications

A new collector undercut process using SiN protection sidewall has been developed for high speed InP/InGaAs single heterojunction bipolar transistors (HBTs). The HBTs fabricated using the technique have a larger base contact area, resulting in a smaller DC current gain and smaller base contact resistance than HBTs fabricated using a conventional undercut process while maintaining low C/sub bc/. Due to the reduced base contact resistance, the maximum oscillation frequency (f/sub max/) has been enhanced from 162 GHz to 208 GHz. This result clearly shows the effectiveness of this technique for high-speed HBT process, especially for the HBTs with a thick collector layer, and narrow base metal width.

Ultra high-speed InP-InGaAs SHBTs with f/sub max/ of 478 GHz

We have developed novel but simple process techniques for high speed InP SHBTs. For parasitic reduction, the collector layer is undercut using an etch-stop layer, the base pad is isolated, and the emitter metal is widened using thick plated gold. For transit time reduction, the SHBT employs InGaAs base with graded In-composition and InGaAlAs emitter setback with graded Al-composition. Maximum extrapolated f/sub max/ of about 687 GHz with f/sub T/ of 215 GHz is achieved for 0.25 /spl times/ 8 /spl mu/m/sup 2/ emitter area devices at I/sub c/ = 8 mA and V/sub ce/ = 15 V. This data clearly shows that the optimized conventional process can offer direct implementation of InP HBT for high-speed electronic circuit fabrication.