Bumman Kim

A fully matched N-way Doherty amplifier with optimized linearity

This paper presents a new fully matched N-way Doherty amplifier. The basic principles of operation and important features are described. For the experimental verification, 2.14-GHz Doherty amplifiers having two-, three-, and four-way structures are implemented using silicon LDMOSFETs and tested using down-link WCDMA signal. The linearity performances of the two-, three-, and four-way Doherty amplifiers are optimized for better efficiency versus linearity by a bias adjustment of the peaking amplifiers. For simultaneously improving the efficiency and linearity to achieve maximum efficiency versus linearity, the gate biases of the peaking amplifiers for the N-way Doherty amplifier are optimized. As a result, the efficiency versus linearity characteristics are drastically improved by N-way extension of the Doherty amplifier.

Optimum operation of asymmetrical-cells-based linear Doherty power Amplifiers-uneven power drive and power matching

We developed a Doherty amplifier with uneven input drive and optimized individual matching for the carrier and peaking cells. In the proposed amplifier, higher input power is delivered to the peaking cell rather than the carrier cell for optimized linear power operation, especially for appropriate load modulation. Both cells are matched differently to further optimize the performance. We analyzed the efficiency of the proposed amplifier as a function of the input drive ratio for the two cells. To interpret the linearity related to the load modulation and harmonic cancellation mechanisms, we simulated the third-order intermodulation amplitude and phase of each cell of the proposed amplifier. For verification, we implemented the asymmetric power amplifier with uneven drive and optimized power matching using Motorolas MRF281SR1 LDMOSFET with a 4-W peak envelope power. For a 2.14-GHz forward-link wireless code-division multiple-access signal, the measured drain efficiency of the amplifier is 40%, and the measured average output power is 33 dBm at an adjacent channel leakage ratio (ACLR) of -35 dBc, while those of the comparable class-AB amplifier are 21% and 30.6 dBm at the same ACLR level, respectively.

Analysis and experiments for high-efficiency class-F and inverse class-F power amplifiers

This paper presents analytic and experimental comparisons for high-efficiency class-F and inverse class-F amplifiers. The analytic formula of the efficiencies, output powers, dc power dissipations, and fundamental load impedances of both amplifiers are derived from the ideal current and voltage waveforms. Based on the formula, the performances are compared with a reasonable condition: fundamental output power levels of class-F and inverse class-F amplifiers are conditioned to be identical. The results show that the inverse class-F amplifier has better efficiency than that of class-F amplifiers as the on-resistance of the transistor increases. For experimental comparison, we have designed and implemented the class-F and inverse class-F amplifiers at I-GHz band using a GaAs MESFET and analyzed the measured performances. Experimental results shows 10% higher power-added efficiency of the inverse class-F amplifier than that of the class-F amplifier, which verifies the waveform analysis.

A Polar Transmitter With CMOS Programmable Hysteretic-Controlled Hybrid Switching Supply Modulator for Multistandard Applications

This paper presents the realization of a linear polar transmitter supporting multistandard applications. The harmonic-tuned class-AB biased (class-AB/F) power amplifier (PA) with the novel envelope shaping method linearly amplifies the input signal with high efficiency. The hybrid switching supply modulator with programmable hysteretic comparator enables the multimode operation whatever the envelope signal characteristics such as the peak-to-average power ratio and the bandwidth are. The designed polar transmitter is fabricated with CMOS 0.13-mum technology and InGaP/GaAs 2-mum HBT process for the supply modulator and the PA, respectively. For the IEEE 802.16e m-WiMax signal, it shows a power-added efficiency (PAE), an average output power (Pout), and a gain of 34.3%, 23.9 dBm, and 27.9 dB, respectively. Without any predistortion techniques, it satisfies the overall spectrum emission mask specifications. The relative constellation error and the error vector magnitude for the m-WiMax signal are -30.5 dB and 2.98%, respectively. For a WCDMA signal, it presents a PAE, a Pout, and a gain of 46%, 29 dBm, and 27.8 dB, respectively. For the EDGE signal, it delivers a PAE of 45.3% at a Pout of 27.8 dBm with a gain of 29.4 dB. There is about a 7% improvement of the overall PAE for EDGE through the optimum multimode operation.

A New Power Management IC Architecture for Envelope Tracking Power Amplifier

A new supply modulator architecture for robust performance against the battery voltage variation is presented. The resulting modulator is an optimized power management integrated circuit (PMIC) for an envelope tracking (ET) power amplifier (PA). The basic topology of the PMIC is based on a hybrid switching amplifier combining a wideband class-AB buffered linear amplifier and a highly efficient switching-mode buck converter in a master-slave configuration. The additional boost converter regulates the supply voltage of the linear amplifier, while the supply of the buck converter is directly coupled to the battery. The proposed supply modulator achieves max/min efficiencies of 76.8/69.3% over the entire battery voltage range. The ET PA is operated at 4.5 V, providing higher output power, efficiency, and gain than at nominal 3.5-V design. The robust performance of the proposed PMIC is demonstrated.

A microwave Doherty amplifier employing envelope tracking technique for high efficiency and linearity

In this letter, we demonstrate a microwave Doherty amplifier employing an input signal envelope tracking technique. In the amplifier, the gate bias of the peaking amplifier is controlled according to the magnitude of the envelope. A 2.14-GHz Doherty amplifier is implemented using 4-W PEP LDMOSFETs, and an adaptive controlled gate bias circuit is constructed and the control shape is optimized experimentally. The performance of the microwave Doherty amplifier is compared with that of a class AB amplifier using one-tone, two-tone, and forward-link wideband code-division multiple access (WCDMA) signals. For a forward-link WCDMA signal, the measured power added efficiency (PAE) of the microwave Doherty amplifier is 39.4% at -30 dBc adjacent channel leakage ratio (ACLR), while that of the comparable class AB amplifier is 24.2% at the same ACLR level.

Adaptive Digital Feedback Predistortion Technique for Linearizing Power Amplifiers

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm

High efficiency and wideband envelope tracking power amplifier with sweet spot tracking

This paper describes the implementation of a high efficiency and wideband envelope tracking power amplifier with sweet spot tracking. By modulating supply voltage of power amplifier (PA), efficiency can be increased significantly. And linearity is improved by envelope shaping and sweet spot tracking. The supply modulator has a combined structure of a switching amplifier and a linear amplifier to achieve high efficiency as well as wide bandwidth. The measurement results show efficiencies of 36.4/34.1 % for 10/20 MHz long term evolution (LTE) signals with peak to average power ratio (PAPR) of 7.5/7.42 dB.

Linearity analysis of CMOS for RF application

The linearity of CMOS has been analyzed using the Taylor series. Transconductance and output conductance are two dominant nonlinear sources of CMOS. At a low frequency, the transconductance is a dominant nonlinear source for a low load impedance, but for a usual operation level impedance the output conductance is a dominant nonlinear source. Capacitances and the substrate network do not generate any significant nonlinearity, but they suppress output-conductance nonlinearity at a high frequency because output impedance is reduced by the capacitive shunts, and output voltage swing is also reduced. Therefore, above 2-3 GHz, the transconductance becomes a dominant nonlinear source for a usual load impedance. If these capacitive elements are tuned out for a power match, the behavior becomes similar to the low-frequency case. As gate length is reduced, the transconductance becomes more linear, but the output conductance becomes more nonlinear. At a low frequency, CMOS linearity is degraded as the gate length becomes shorter, but at a higher frequency (above 2-3 GHz), linearity can be improved.

A highly linear and efficient differential CMOS power amplifier with harmonic control

A 2.45 GHz fully differential CMOS power amplifier (PA) with high efficiency and linearity is presented. For this work, a 0.18-/spl mu/m standard CMOS process with Cu-metal is employed and all components of the two-stage circuit except an output transformer and a few bond wires are integrated into one chip. To improve the linearity, an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node is adopted along with normal harmonic termination at the drain. The harmonic termination at the source effectively suppresses the second harmonic generated from the input and output. The amplifier delivers a 20.5dBm of P/sub 1dB/ with 17.5 dB of power gain and 37% of power-added efficiency (PAE). Linearity measurements from a two-tone test show that the power amplifier with the second harmonic termination improves the IMD3 and IMD5 over the amplifier without the harmonic termination by maximally 6 dB and 7 dB, respectively. Furthermore, the linearity improvements appear over a wide range of the power levels and the linearity is maintained under -45 dBc of IMD3 and -57dBc of IMD5 when the output power is backed off by more than 5dB from P/sub 1dB/. From the OFDM signal test, the second harmonic termination improves the error vector magnitude (EVM) by over 40% for an output power level satisfying the 4.6% EVM specification.