Daewook Kim

CDMA-based network-on-chip architecture

We present a network-on-chip (NoC) architecture that is based on code division multiple access (CDMA) techniques. The orthogonality properties of a Walsh code are used to route data packets between resources. A star network topology allows a hierarchical switching platform to be constructed which can be scaled to handle large systems. The switching element and network topology are described and algorithms for modulation and demodulation of packets are presented. Simulation results for throughput and latency are given.

Network-on-chip link analysis under power and performance constraints

This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links between adjacent routers and links between a router and an attached processing element (PE). Analytical models for global router-to-router links and semi-global router-to-PE links are studied. Power and performance optimizations are obtained for each of these two classes of interconnections

MPEG-4 performance analysis for a CDMA network-on-chip

Realistic traffic patterns for a multi-processor MPEG-4 architecture are used to evaluate the performance of network-on-chip (NoC) implementations. In particular, we study the characteristics for a design that is based on CDMA switching techniques and a star-network topology. The results are compared to those for a more conventional mesh-topology NoC. We evaluate metrics for bandwidth requirements, latency and area overhead and show that the CDMA star design is a good candidate for the implementation of these systems.

Network-on-chip quality-of-service through multiprotocol label switching

Providing quality-of-service (QoS) in networks-on-chip (NoCs) is an important consideration for the complex multiprocessor chips of the future. In this paper, we discuss the difficulties encountered in addressing these requirements. Then, we propose a promising solution to this problem that is based on applying the well-known MPLS technology of large-scale computer networks to the on-chip environment. A network simulator is used to evaluate the concept for a typical communications scenario that must support several classes of traffic having a range of QoS requirements

Adaptive scheduling for CDMA-based networks-on-chip

A novel adaptive scheduling algorithm for CDMA-based networks-on-chip is proposed. An orthogonal variable spreading factor (OVSF) code is combined with the dual round robin matching (DRRM) algorithm to obtain efficient usage of orthogonal codewords. The length of codewords is adjusted depending on how many active IP blocks have packets to send at any given time. In addition, pointers are maintained to perform the necessary input and output arbitration. SystemC simulation results demonstrate that our scheduling technique exhibits the fairness property.

NIUGAP: low latency network interface architecture with Gray code for networks-on-chip

The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP cores. In this paper, we present a novel NIU architecture that utilizes a Gray code based packet reordering methodology to achieve low latency packet processing. The proposed architecture has been implemented with VHDL and synthesized using a 0.25 mum ASIC technology. Simulation results verify the functionality of the architecture and show that it can save a substantial amount of packet processing time compared to the conventional reordering scheme

Parallel FFT computation with a CDMA-based network-on-chip

Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations. We present two methodologies for mapping an FFT computation onto a CDMA-based star topology network-on-chip (NoC) architecture. These implementations reduce the FFT data shuffling time and simplify the data flow between processing elements. The design has been modeled using SystemC and the simulation results provide throughput and latency performance metrics for the different mapping scenarios.

FPGA-based CDMA switch for networks-on-chip

This paper presents timing and area results for an FPGA implementation of a CDMA-based switch for networks-on-chip. The design was mapped onto the Xilinx Virtex4 XC4VLX200 device using Synplify Pro for a range of pay-load sizes. The synthesis results give the area and maximum frequency obtained. Simulation verifies the desired functionality and provides throughput and latency values as functions of payload size.

DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs

Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection networks plays a critical role in shared memory MPSoC designs. In this paper, we propose a directory-cache embedded switch architecture with distributed shared cache and distributed shared memory. It is able to reduce the number of home node cache accesses, which results in a reduction in the inter-cache transfer time and the total execution time. Simulation results verify that the proposed methodology can improve performance substantially over a design in which directory caches are not embedded in the switches