Gerald E. Sobelman

CMOS circuit design of threshold gates with hysteresis

M-of-N threshold gates with hysteresis form a class of circuit elements that have important application in NULL Convention Logic/sup TM/, a novel asynchronous logic design methodology. General design guidelines for these M-of-N gates are presented using CMOS technology. Three types of circuit implementations are discussed: static, semi-static and dynamic. In addition, initialization techniques are presented for use in establishing a known initial state.

Architectures for multi-gigabit wire-linked clock and data recovery

Clock and data recovery (CDR) architectures used in high-speed wire-linked communication receivers are often shown as PLL or DLL based topologies. However, there are many other types of CDR architectures such as phase-interpolator, oversampling and injection locked based topologies. The best choice for the CDR topology will depend on the application and the specification requirements. This paper presents an overview and comparative study of the most commonly used CDR architectures. This analysis includes the circuit structures, design challenges, major performance limitations and primary applications. Finally, the tradeoffs among the various CDR architectures are summarized.

Elliptic Curve Scalar Multiplier Design Using FPGAs

A compact fast elliptic curve scalar multiplier with variable key size is implemented as a coprocessor with a Xilinx FPGA. This implementation utilizes the internal SRAM/registers of the FPGA and has the whole scalar multiplier implemented within a single FPGA chip. The compact design helps reduce the overhead and limitations associated with data transfer between FPGA and host, and thus leads to high performance. The experimental data from the mappings over small fields shows that the carefully constructed hardware architecture is regular and has high CLB utilization.

Low-power multiplier design using delayed evaluation

A circuit design technique for very low power parallel multipliers is presented. The design uses dynamic CMOS circuits together with a self-timed evaluate signal in such a way that each carry-save or carry-propagate adder within the array evaluates only after all of its inputs have stablized. This technique avoids the spurious switching of internal nodes so that the average power dissipation is minimized. Circuit simulation results are presented which illustrate the power dissipation characteristics of the multiplier.

CDMA-based network-on-chip architecture

We present a network-on-chip (NoC) architecture that is based on code division multiple access (CDMA) techniques. The orthogonality properties of a Walsh code are used to route data packets between resources. A star network topology allows a hierarchical switching platform to be constructed which can be scaled to handle large systems. The switching element and network topology are described and algorithms for modulation and demodulation of packets are presented. Simulation results for throughput and latency are given.

A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes

A reduced-complexity low density parity check (LDPC) layered decoding architecture is proposed using an offset permutation scheme in the switch networks. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, we use a block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput. The proposed architecture is realized for a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device. The design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz with a maximum of 8 iterations.

FPGA-based FIR filters using digit-serial arithmetic

This paper describes the use of digit-serial arithmetic for compact and efficient implementations of real-time DSP applications on field programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR filter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR filters is described. The results show that digit-serial designs with a digit-size of 2 bits have about 17% smaller area-time product than those of a bit-serial implementations.

A compact fast variable key size elliptic curve cryptosystem coprocessor

Elliptic curve (EC) cryptosystems have become more attractive due to their small key sizes and varieties of choices of the curves available. However, it is not efficient to implement them with a general-purpose microprocessor because of word size mismatch, less parallel computation, no hardware supported wire permutation and algorithm/architecture mismatch. The solution to this problem is to build a coprocessor. This coprocessor can be optimized for the algorithm of a particular application to enhance performance. Thus, the total hardware utilization can be kept at a very high rate and the computation is speeded up. A compact fast elliptic curve crypto coprocessor with variable key size is introduced, which utilizes the internal SRAM/registers in an FPGA. The generic hardware architecture for the coprocessor is implemented with a parameterized (in term of key size) VHDL description and is synthesized/mapped to a Xilinx FPGA. The algorithms adopted and the architecture developed are suitable for massively parallel computation. The experimental results show that the design can achieve a high utilization of CLBs for the Xilinx 4000 series.

A new low-voltage full adder circuit

A new circuit based on combining XOR gates and double pass-transistor logic has been developed for implementing a full adder. The main design objectives for these new circuits are low power consumption and full-voltage swing at a low supply voltage. The proposed full adder circuit is compared with previously known circuits and is shown to provide superior performance. The new and previous full adder circuits have been fully simulated using HSPICE with 0.4 /spl mu/m CMOS technology at a 2.0 V supply voltage. An extensive analysis of a 8-bit carry-select adder establishes the superiority of the proposed circuit in that application.

Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an enhanced delay element matrix structure, which supports 25-, 16-, 9-, 8-, 5-, 4-, 3-, and 2-point FFTs. Two different designs were implemented. One design (called discrete Fourier transform core) supports 34 different transform sizes from 12 to 1296 points, while the other design (called FFT core) supports five different power-of-two sizes from 128 to 2048 points. The 1-D factorization method is performed by a coprime accessing technology, which accesses the data in parallel without conflict using a RAM. The GHR combines 2-D and 1-D factorization techniques and improves the throughput by a factor of two to four with comparable hardware cost compared with the previous designs. The speed-area ratio of the proposed scheme is nearly two times better than that of previous FFT processors. Application-specified integrated circuit implementation results based on a 0.18-μm technology are also provided.