Dahai Huang

Study of turn-on characteristics of SCRs for ESD protection with TDR-O and TDR-S TLPs

There are few good evaluation methods to evaluate CDM ESD protection performance such as device turn-on speed, etc. A new current-waveform-based method to evaluate the turn-on speed of an ESD protection device is proposed. The method uses two Transmission-Line Pulse (TLP) Tester to investigate the turn-on characteristics of SCR and related devices. Both intrinsic and normalized turn-on conditions are defined for protection devices to study the different factors that affect the turn-on characteristic under various conditions. The turn-on of both forwardly and reversely working of devices is measured for the CDM model including positive and negative currents. From the experimental results, it is concluded that NMLSCRs performance is superior to PMLSCR in turn-on speed; MLSCR requires higher It1 to be turned on; and the turn-on speed of a PMLSCR decreases significantly with small increases in pulse amplitude under intrinsic working condition while NMLSCR and LSCR do not exhibit such property.

Investigation of turn-on speeds of electrostatic discharge protection devices using transmission-line pulsing technique

As process technologies advance into deep sub-micrometer and nanometer scale, the charged device model (CDM) is now considered an important stress model for defining electrostatic discharge (ESD) reliability of integrated circuits. Thus the turn-on time of the ESD elements used in the protection circuit becomes important. At this time, there is no good method to evaluate the CDM ESD device turn-on speed. Equipment like VF-TLP and CC-TLP are too complicated and not precise for this purpose. A new method to evaluate the ESD device turn-on speed is presented in this paper. Based on this novel approach, some CDM ESD devices are analyzed based on the transmission line pulsing (TLP) tester. The designed devices include diodes, grounded-gate NMOS, SCRpsilas (silicon controlled rectifier), and Modified-Lateral SCRpsilas (MLSCR). The rising time of the pulse is set at 200 psec to accurately simulate real CDM pulses. The time-dependent voltage and current data are extracted and calculated from each pulse in the Time Domain Reflection (TDR) TLP tester. Two new ESD turn-on conditions are proposed and defined based on the transient currents in order to compare the relative speed of different ESD devices. The results show that the normalized turn-on time of different devices with various sizes and finger numbers do not correlate well with that obtained under the normal DC conditions, and the same device shows different turn-on characteristics under different pulses. These results enable devices to be designed for improved CDM ESD protection levels, and the present method can be used for ESD design for future nanometer technologies.

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

Abstract Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time.

Effects of process variation on turn-on voltages of a multi-finger gate-coupled NMOS ESD protection device

The popular electrostatic discharge (ESD) protection device, multi-finger NMOS with gate-coupling technique for better uniform turning-on, can be affected by process variation. The transmission line pulsing (TLP) test results reveal this phenomenon. The trigger voltage of the same pin on some products shifts from 9.5V to 15.5V. No such significant difference was ever reported in the literature. In this study, the circuit simulations at various process corners are applied to study the snapback device under this situation. With only the NMOS gate-drain overlap as coupling capacitance, the gate-to-ground resistor plays a vital role in counteracting the variation. When increased from 3KOhm to 12KOhm, the turn-on voltage is reduced and the target ESD performance is achieved. The protection structure is processed on an EEPROM process, which is used as both I/O protection circuit and power-clamp. It is able to pass 4KV HBM ESD level.

Design analysis of novel substrate-triggered GGNMOS in 65nm CMOS process

A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65nm CMOS process. The trigger voltage can be significantly reduced to ㌬3V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin gate. The uniform conducting between multi-fingers has greatly enhanced and the failure current can effectively improved by 23.5%