Qiang Cui

Investigation of turn-on speeds of electrostatic discharge protection devices using transmission-line pulsing technique

As process technologies advance into deep sub-micrometer and nanometer scale, the charged device model (CDM) is now considered an important stress model for defining electrostatic discharge (ESD) reliability of integrated circuits. Thus the turn-on time of the ESD elements used in the protection circuit becomes important. At this time, there is no good method to evaluate the CDM ESD device turn-on speed. Equipment like VF-TLP and CC-TLP are too complicated and not precise for this purpose. A new method to evaluate the ESD device turn-on speed is presented in this paper. Based on this novel approach, some CDM ESD devices are analyzed based on the transmission line pulsing (TLP) tester. The designed devices include diodes, grounded-gate NMOS, SCRpsilas (silicon controlled rectifier), and Modified-Lateral SCRpsilas (MLSCR). The rising time of the pulse is set at 200 psec to accurately simulate real CDM pulses. The time-dependent voltage and current data are extracted and calculated from each pulse in the Time Domain Reflection (TDR) TLP tester. Two new ESD turn-on conditions are proposed and defined based on the transient currents in order to compare the relative speed of different ESD devices. The results show that the normalized turn-on time of different devices with various sizes and finger numbers do not correlate well with that obtained under the normal DC conditions, and the same device shows different turn-on characteristics under different pulses. These results enable devices to be designed for improved CDM ESD protection levels, and the present method can be used for ESD design for future nanometer technologies.

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

Abstract Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time.

Robustness evaluation of ESD protection devices in NEMS using a novel TCAD methodology

Robustness performance is one of the most important concerns in the design of ESD (electro-static discharge) protection devices, and this quality plays a more and more important role in NEMS protection devices. Improvement of robustness requires not only experience but also TCAD (technology computer aided design) methodology to evaluate ESD protection devices in NEMS. A novel TCAD methodology for robustness evaluation is presented and developed here. This methodology is based on mix-mode transient circuit simulation, and this simulation method depicts ESD events better. Through analyse of the time effect on power accumulation, an important key parameter, named as robustness coefficient, is provided to characterize and evaluate robustness performance of ESD protection devices quantificationally. Based on analyse of this robustness coefficient of different ESD devices under different ESD models and levels, the results show that this TCAD methodology has a good ability of convergence, and can be used to evaluate robustness performance of ESD protection devices objectively.

Investigation of waffle structure SCR for electro-static discharge (ESD) protection

The waffle layout SCR-based ESD protection device is presented and analyzed in this paper. This waffle structure with symmetrical layout is designed to generate more current paths to distribute ESD currents better. TLP I-V measurement results show that, the stand-alone waffle layout SCR costs only 39 percent silicon area of conventional stripe layout SCR, but can achieve better ESD robustness. Results also show that the trigger voltage and current handling ability of waffle layout SCR can be adjustable to meet different operating demands by changing the device dimensions.

A novel SCR for ESD protection in ICs

A novel silicon controled rectifiers (SCR) is presented in this paper. This SCR, named as HH-LVTSCR, is characterized as high holding voltage and low trigger voltage. Through measuring the current versus voltage (I-V) by TLP, this SCRs properties, including trigger voltage, holding voltage and failure current, are investigated. Results show that this SCR has a good electrostatic discharge (ESD) protection performance for integrated circuits (ICs). Further more, this SCRs I-V is insightfully analyzed, such as the relationship between failure current and holding voltage, the effects of ambient temperature on holding voltage and trigger voltage, the effects of multiple-finger layout on the performance of devices. The results suggest that n-type devices perform better than p-type devices when a low holding voltage(VH) is demanded ,however p-type devices perform better while a relatively high holding voltage is required.

Analyse of Protection Devices' Speed Performance against ESD under CDM Using TCAD

Speed performance plays a critical role in protection devices against ESD (Electro-Static Discharge) overstress under CDM (Charged Device Model). It is too demanding to obtain speed performance of protection devices under CDM accurately by testing. Therefore we have to resort to TCAD (Technology Computer Aided Design) method to evaluate speed performance under CDM. This TCAD methodology is based on mix-mode transient circuit simulation, which depicts ESD events better. Two time constants, Ttrigger and Trecover, and two key coefficients, Ftrigger and Crecover, are provided to characterize and evaluate speed performance of ESD protection devices. The results show that this TCAD methodology has a good ability of convergence and is a good tool to evaluate speed performance of ESD protection devices quantificationally. Anlayse results show that speed performance of SCR is superior over ggNMOS in not only triggering but also bypassing ESD currents to recover the voltage towards a safe level.