Dajie Zeng

A 60GHz wideband injection-locked frequency divider with adaptive-phase-enhancing technique

A 60-GHz injection-locked frequency divider (ILFD) with quadrature outputs is designed in 90-nm CMOS technology. An adaptive-coupling scheme is proposed to enlarge the phase shift for a wide-band locking range. The measured results exhibit an input locking range of 12.1GHz or 20.5%from 52.7 to 64.8GHz at an incident power of 0dBm. The core circuit consumes 8.6mW from a 1.2V power supply and occupies an area of 360µm×230µm2.

A unified model for on-chip CPWs with various types of ground shields

Coplanar waveguides (CPW) are promising candidates for high quality passive devices in millimeter-wave frequency bands. In this paper, CPW transmission lines with and without ground shields have been designed and fabricated on 65nm CMOS technology. A physical-based model is proposed to describe the frequency-dependent per-unit-length L, C, R, and G parameters. Started from a standard CPW structure, influences of different kinds of ground shields have been analyzed and included into the general model. The accuracy of the model is confirmed by experimental results.

Understanding dynamic behavior of mm-wave CML divider with injection-locking concept

An analytical framework has been developed to describe the locking behavior of millimeter (mm) wave current-mode logic (CML) frequency divider. Unlike traditional analysis based on RC delay, the proposed model is established with injection-locking concept from analog perspective. Both analytical formulas and graphic interpretation are provided for design insights. The model has been validated by exhaustive simulations and important guidelines have been concluded for circuit design.

Modeling of Current-Return-Path Effect on Single-Ended Inductor in Millimeter-Wave Regime

The effect of current return path (CRP) on the accurate modeling of single-ended inductors in the millimeter-wave regime has been investigated. A series of spiral inductors with different sizes, shapes, and CRP positions was fabricated in a 0.18-μm RF-CMOS process and measured up to 50 GHz. An analytical appended model for CRP is developed to characterize the effect, and its equivalent circuit is validated by measurement results. The proposed model can help millimeter-wave circuit designers to devise layout routing flexibly with high accuracy.

Design of a 24GHz low phase-noise,wide tuning-range VCO with optimized switches in capacitor array and bias filtering technique

A low phase-noise 24GHz VCO (voltage-controlled oscillator) for mm-wave WLANs (wireless LANs) using IBM 90nm CMOS process is presented. A current source is used to minimize the impact due to the process variation. Biasing filter technique is adopted to improve the phase noise performance. In addition, optimized switches are proposed to prevent phase noise degradation. Simulation shows that −101dBc/Hz phase noise is achieved at 1MHz offset. The tuning range of the VCO spans from 24.2GHz to 29.1GHz. Total power consumption of the VCO core is 2.8mW from 0.8V supply.

A novel equivalent circuit for on chip transmission lines modeling

Microstrip transmission line (MS), coplanar waveguide transmission line (CPW), grounded coplanar waveguide transmission line (GCPW), slow-wave transmission line with slotted grounded shields (GSCPW), slow-wave transmission line with slotted floating shields (FSCPW) are widely used in the silicon technology. Because the quasi-TEM assumption is still valid in these structures, an equivalent circuit is proposed to model all these structures. In this work, we notice that for some types of transmission lines, say GCPW and GSCPW, the per unit length capacitance increases with frequency. An LC series subcircuit is proposed to model this phenomenon. For CPW, GCPW, GSCPW and FSCPW, the model has very good accuracy and fits the measurement results very well up to the highest measurement frequency (40GHz). For MS, the results from the 3D EM simulation software are adopted and the model shows a great agreement with the simulation results up to the highest simulation frequency (100GHz).

An inductorless wideband low noise amplifier with current reuse and linearity enhancement

In this paper, a wide-band inductor-less LNA for low voltage operation is presented. The input matching is implemented by using a feedback transistor with a resistor terminated to the source to enhance linearity and to reduce noise. Current reuse technique is employed to increase the total transconductance. Under 1V supply voltage and a DC of 5.6 mA, the LNA achieves an average noise figure of 3.2 dB, a maximum voltage gain of 18.6 dB, and 3 dB bandwidth ranges from 0.2-4.5 GHz.

A low-power ESD-protected 24GHz receiver front-end with π-type input matching network

This paper presents a full ESD-protected receiver front-end for wireless communications around 24GHz, comprising LNA, mixer, VGA, and on-chip balun. A π-type input matching network incorporating ESD capacitance is constructed to realize the source impedance transformation for higher gain. With it, the gain of the first stage is improved while the noise figure is just degraded slightly. The measured results show an input return loss of less than −12dB, 36dB voltage gain, 6.9dB noise figure, and 2dBm output P1dB. The chip has an HBM ESD robustness of ±2kV and consumes 34mA from a 1.2V supply with a total area of 1×0.8 mm2 using 0.13µm RF CMOS process.

Design of a 24GHz wide tuning-range VCO with optimized switches in resonator

A wide tuning range 24GHz VCO (voltage-controlled oscillator) using IBM 90nm CMOS process is presented. Switched inductor and two bits capacitance array offer a widely tuning range. In addition, optimized switches are adopted to improve both tuning range and phase noise performance. Simulation shows that −101dBc/Hz phase noise is achieved at 1MHz offset. The tuning range of the VCO spans from 21.9GHz to 27.1GHz. Total power consumption of the VCO core is 3.3mW from 0.8V supply.

Robust spatial correlation extraction with limited sample via L1-norm penalty

Random process variations are often composed of location dependent part and distance dependent correlated part. While an accurate extraction of process variation is a prerequisite of both process improvement and circuit performance prediction, it is not an easy task to characterize such complicated spatial random process from a limited number of silicon data. For this purpose, kriging model was introduced to silicon society. This work forms a modified kriging model with L1-norm penalty which offers improved robustness. With the help of Least Angle Regression (LAR) in solving a core optimization sub-problem, this model can be characterized efficiently. Some promising results are presented with numerical experiments where a 3X improvement in model accuracy is shown.