Dale C. Morris

Introducing the IA-64 architecture

Microprocessors continue on the relentless path to provide more performance. Every new innovation in computing-distributed computing on the Internet, data mining, Java programming, and multimedia data streams-requires more cycles and computing power. Even traditional applications such as databases and numerically intensive codes present increasing problem sizes that drive demand for higher performance. Design innovations, compiler technology, manufacturing process improvements, and integrated circuit advances have been driving exponential performance increases in microprocessors. To continue this growth in the future, Hewlett Packard and Intel architects examined barriers in contemporary designs and found that instruction-level parallelism (ILP) can be exploited for further performance increases. This article examines the motivation, operation, and benefits of the major features of IA-64. Intels IA-64 manual provides a complete specification of the IA-64 architecture.

Pathlength reduction features in the PA-RISC architecture

A description is given of representative pathlength reduction features of PA-RISC (reduced instruction set computer) instructions in memory accessing, functional operations, and instruction sequencing. To illustrate the multi-op instructions in PA-RISC, comparison is made with the MIPS instruction set, rather than with some hypothetical single-op RISC instructions. It is noted that, while other RISC architectures strive to enable short cycle times and single cycle instruction execution, PA-RISC also supports pathlength reduction, without impacting either the cycle time or the CPI. Frequent operations are combined into a single multi-op instruction. Subword data are also operated on in parallel, making full use of the datapath width. Such instruction level parallelism gives PA-RISC some of the advantages of a very simple VLIW (very long instruction word) architecture (with short 32-b instructions), in addition to the inherent advantages of a streamlined RISC architecture.<<ETX>>

OS and compiler considerations in the design of the IA-64 architecture

Increasing demands for processor performance have outstripped the pace of process and frequency improvements, pushing designers to find ways of increasing the amount of work that can be processed in parallel. Traditional RISC architectures use hardware approaches to obtain more instruction-level parallelism, with the compiler and the operating system (OS) having only indirect visibility into the mechanisms used.The IA-64 architecture [14] was specifically designed to enable systems which create and exploit high levels of instruction-level parallelism by explicitly encoding a programs parallelism in the instruction set [25]. This paper provides a qualitative summary of the IA-64 architecture features that support control and data speculation, and register stacking. The paper focusses on the functional synergy between these architectural elements (rather than their individual performance merits), and emphasizes how they were designed for cooperation between processor hardware, compilers and the OS.