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Stephen G. Burger

Hewlett-Packard

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Publication

Featured researches published by Stephen G. Burger.

Archive | 2001

Method and apparatus for pre-validating regions in a virtual addressing scheme

Stephen G. Burger; James O. Hays; Jonathan K. Ross; William R. Bryg; Rajiv Gupta; Gary N. Hammond; Koichi Yamada

Archive | 1998

Apparatus and method for a virtual hashed page table

William R. Bryg; Stephen G. Burger; James O. Hays; John M. Kessenich; Jonathan K. Ross; Gary N. Hammond; Sunil Saxena; Koichi Yamada

Archive | 1999

Method and apparatus for calculating a page table index from a virtual address

William R. Bryg; Stephen G. Burger; Gary N. Hammond; James O. Hays; Jerome C. Huck; Jonathan K. Ross; Sunil Saxena; Koichi Yamada

Archive | 1994

Access hints for input/output address translation mechanisms

K Monroe Bridges; Robert J. Brooks; William R. Bryg; Stephen G. Burger; Eric W. Hamilton; Helen Nusbaum; Brendan A. Voge; Michael L. Ziegler

Archive | 1997

Computer architecture for the deferral of exceptions on speculative instructions

Jonathan K. Ross; Jack D. Mills; James O. Hays; Stephen G. Burger; Dale C. Morris; Carol L. Thompson; Rajiv Gupta; Stefan M. Freudenberger; Gary N. Hammond; Ralph M. Kling

Archive | 1997

Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address

Koichi Yamada; Gary N. Hammond; Jim Hays; Jonathan Kent Ross; Stephen G. Burger; William R. Bryg

Archive | 1998

Apparatus and method for a load bias--load with intent to semaphore

William R. Bryg; Stephen G. Burger; Gary N. Hammond; Michael L. Ziegler

Archive | 1995

Computer apparatus having special instructions to force ordered load and store operations

Dale C. Morris; Barry J. Flahive; Michael L. Ziegler; Jerome C. Huck; Stephen G. Burger; Rugby B.L. Lee; Bernard Stumpf; Jeff Kurtze

Archive | 1994

Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache

K Monroe Bridges; William R. Bryg; Stephen G. Burger; James M. Hull; Michael L. Ziegler

Archive | 1997

Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory

Dale C. Morris; Bernard Stumpf; Barry J. Flahive; Jeffrey D. Kurtze; Stephen G. Burger; Ruby B. Lee; William R. Bryg

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Collaboration

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William R. Bryg

Hewlett-Packard

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Michael L. Ziegler

Hewlett-Packard

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Gary N. Hammond

Intel

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Dale C. Morris

Hewlett-Packard

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Jerome C. Huck

Hewlett-Packard

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Jonathan K. Ross

Hewlett-Packard

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James O. Hays

Intel

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K Monroe Bridges

Hewlett-Packard

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Koichi Yamada

Intel

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Ruby B. Lee

Princeton University

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