Dale E. Hoffman

Design methodology for the S/390 parallel enterprise server G4 microprocessors

This paper describes the design methodology employed in the design of the S/390® Parallel Enterprise Server G4 microprocessors. Issues of verifying design metrics of area, power, noise, timing, testability, and functional correctness are discussed within the context of a transistor-level custom design approach. Practical issues of managing the complexity of a 7.8-million-transistor design and encouraging design productivity are introduced.

Advanced microprocessor test strategy and methodology

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBMs high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

Testing the 400 MHz IBM generation-4 CMOS chip

This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level.

250-MHz advanced test systems

New generations of electronic chips bring with them the promise of more capacity, storage, and speed. They also bring new challenges to design, test and manufacturing. A look at a series of advanced test systems, how they were designed and why, sheds new light on this practical side of advanced technology. These test systems are the ATS series from IBM.<<ETX>>

Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor

High frequency microprocessor designs require rigorous design guidelines, design methodology advancements, and novel approaches in circuit design style for processors operating in the high megahertz range. Timing closure becomes the single most important design issue, however other design metrics such as area, power and noise need to be given equal consideration within the design cycle. Custom design techniques were used through out the logic circuits and arrays as well as the overall design planning for the 500 MHz microprocessor cycle time.

Testing the 500-MHz IBM S/390 microprocessor

The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.

A 1.1 GHz first 64 b generation 2900 microprocessor

The first 64 b S/390 microprocessor implemented in a 0.18 /spl mu/m, 7-level copper interconnect bulk CMOS process, runs operating system and applications at 1.1 GHz. The frequency is achieved with interconnect width and repeater optimization, selective use of low-Vt devices, tapered library gates, and improved synthesis and circuit tuning algorithms.