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Dive into the research topics where Dale Greenley is active.

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Featured researches published by Dale Greenley.


design automation conference | 1995

UltraSPARC-I

James Gateley; Miriam Blatt; Dennis Chen; Scott Cooke; Piyush Desai; Manjunath Doreswamy; Mark Elgood; Gary F. Feierbach; Tim Goldsbury; Dale Greenley

The next generation UltraSPARC-I CPU represents a significant step forward in processor performance at the cost of increased design complexity. Added complexity increases the risks in achieving functionally correct first silicon. Existing design verification techniques were supplemented by applying emulation to obtain an early look at functionality. Discussed are the goals, methods and results of the UltraSPARC-I emulation.


COMPCON '96. Technologies for the Information Superhighway Digest of Papers | 1996

UltraSPARC: compiling for maximum floating-point performance

Partha P. Tirumalai; Dale Greenley; Boris Beylin; Krishna Subramanian

UltraSPARC-I is the first microprocessor from Sun Microsystems to implement the new 64-bit SPARC V9 architecture. UltraSPARC-I is a superscalar processor capable of issuing up to four instructions together and possesses several features designed to enable high performance on a variety of applications. While UltraSPARC-I maintains strict binary compatibility with and delivers excellent performance on thousands of existing 32-bit applications developed for other SPARC processors, even more benefit can be derived by using a compiler that specifically targets it. This paper discusses various features of UltraSPARC-I and the compiler techniques used to leverage them to obtain high performance on many floating point programs.


ieee computer society international conference | 1995

UltraSPARC: the next generation superscalar 64-bit SPARC

Dale Greenley; J. Bauman; D. Chang; Dennis Chen; R. Eltejaein; P. Ferolito; P. Fu; Robert B. Garner; D. Greenhill; H. Grewal; Kalon Holdbrook; Byungsuk Kim; Leslie Kohn; H. Kwan; M. Levitt; Guillermo Maturana; D. Mrazek; Chitresh Chandra Narasimhaiah; Kevin Normoyle; N. Parveen; P. Patel; A. Prabhu; Marc Tremblay; Michelle Wong; L. Yang; Krishna C. Yarlagadda; Robert K. Yu; Robert Yung; Gregory B. Zyner


Archive | 1995

Methods and apparatuses for servicing load instructions

Dale Greenley; Leslie Kohn; Ming Yeh; Greg Williams


Proceedings of the IEEE | 1995

The design of the microarchitecture of UltraSPARC-I

Marc Tremblay; Dale Greenley; Kevin Normoyle


Archive | 1995

Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses

Leslie Kohn; Ken Okin; Dale Greenley


Archive | 1997

Hit bit for indicating whether load buffer entries will hit a cache when they reach buffer head

Dale Greenley; Leslie Kohn; Ming Yeh; Greg Williams


Archive | 1996

Dynamic priority switching of load and store buffers in superscalar processor

Dale Greenley; Leslie Kohn


Archive | 1997

Apparatus and method for write miss processing in a copy-back data cache with an allocating load buffer and a non-allocating store buffer

Bruce Petrick; Dale Greenley


Archive | 2000

Automatic delay element insertion system for addressing holdtime problems

Le Quach; Lakshminarasimhan Varadadesikan; Dale Greenley

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