Kevin Normoyle

UltraSPARC-II/: expanding the boundaries of a system on a chip

This processor uses a significant amount of integration and other techniques to enable the construction of cost-efficient SPARC computer systems that retain excellent absolute performance.

Innovative Verification Techniques Used in the Implementation of a Third-Generation 1.1GHz 64b Microprocessor

A third-generation 1.1 GHz 64b microprocessor provides 1 MB on-chip L2

Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system

, 4GB/s off chip memory bandwidth and a 200MHz JBUS interface that supports 1 to 4 processors. The 90M transistor chip is implemented in a 7-level metal copper 0.13/spl mu/m CMOS process and dissipates 53W at 1.3V and 1.1GHz.