Dalibor F. Vrsalovic
Carnegie Mellon University
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Featured researches published by Dalibor F. Vrsalovic.
ieee international symposium on fault tolerant computing | 1988
Zary Segall; Dalibor F. Vrsalovic; Daniel P. Siewiorek; David A. Yaskin; J. Kownacki; James H. Barton; R. Dancey; A. Robinson; Ting-Ting Y. Lin
An automated real-time distributed accelerated fault injection environment (FIAT) is presented as an attempt to provide suitable tools for the validation process. The authors present the concepts and design, as well as the implementation and evaluation of the FIAT environment. As this system has been built, evaluated and is currently in use, an example of fault tolerant systems such as checkpointing and duplicate and match is used to show its usefulness.<<ETX>>
IEEE Computer | 1989
Ted Lehr; Zary Segall; Dalibor F. Vrsalovic; Eddie Caplan; Alan L. Chung; Charles E. Fineman
The authors examine a special software development environment called the Parallel Programming and Instrumentation Environment (PIE). PIE is designed to develop performance-efficient parallel and sequential computations. Following an explanation of PIEs general theory and features, PIEs visualization tools are used to isolate and repair the parallelism problem of an eight-process computation. Two more difficult examples using PIE are discussed. Some of the issues involved in correctly presenting visual information, such as the features users ask for and what can be done about a performance monitors perturbation of computations, are addressed.<<ETX>>
IEEE Transactions on Computers | 1988
Dalibor F. Vrsalovic; Daniel P. Siewiorek; Zary Segall; Edward F. Gehringer
A model for predicting multiprocessor performance on iterative algorithms is developed. Each iteration consists of some amount of access to global data and some amount of local processing. The iterations may be synchronous or asynchronous, and the processors may or may not incur waiting time, depending on the relationship between the access time and processing time. The effect on performance of the speed of the processor, memory, and the interconnection network is studied. The model also illustrates the significant impact on performance of decomposing an algorithm into parallel processes. The models predictions are calibrated with experimental measurements. >
hawaii international conference on system sciences | 1989
Nino Vidovic; Daniel P. Siewiorek; Dalibor F. Vrsalovic; Zary Segall
A description is given of the issues encountered in generating an integrated design environment (IDE) based on the DEMETER workbench (DWB) and PIE (a parallel programming and instrumentation environment for UNIX machines). Some of the reasons for using a general integration methodology are explained. DEMETER, which supports complexity reduction, CAD tools management and manipulation, and distributed/parallel problem-solving, is presented. DWB is described. It is shown how the IDE can be built using the DWB and the basic concepts developed in PIE.<<ETX>>
conference on high performance computing (supercomputing) | 1990
Manohar Rao; Zary Segall; Dalibor F. Vrsalovic
An approach for efficiently mapping parallel applications onto parallel MIMD machine architectures is introduced. The applicability of this approach to uniform memory-access multiprocessors is demonstrated. It is shown that an intermediate layer of abstraction between the application level and the parallel architecture level is conducive not only to a better software productivity but also to performance efficient programs. The intermediate layer consists of a set of commonly used parallel programming paradigms (implementation machines). A mathematical representation and a pragmatic representation are provided for each implementation machine (IM). The user maps the application onto one or a set of IMs and the system implements the IMs efficiently on the underlying parallel machine.<<ETX>>
ieee computer society international conference | 1990
Dalibor F. Vrsalovic; Zary Segall; Jim Ready
This paper addresses the problem of ascertaining the quantitative properties of dependable distributed/parallel systems. The approach is based on fault injection technology developed on the FIAT project. Experimental results are presented which indicate dependability properties (e.g. error detection coverage, error latency) based on a limited number of fault injections.<<ETX>>
hawaii international conference on system sciences | 1989
Dalibor F. Vrsalovic; Zary Segall; D. Seiwiorek; F. Gregoretti; Eddie Caplan; C. Fineman; S. Kravitz; Ted Lehr; M. Russinovitch
Multiprocessor C (MPC), a C language preprocessor that assists a programmer in building efficient parallel programs, is described. MPC provides the programmer with a virtual implementation machine, the consistent abstract shared data type implementation machine (CASDTIM). The machine is described and an analytical model for predicting performance of MPC programs using the CASDTIM is presented. The analytic model is shown to be in close agreement with the measurements of an actual MPC program executing on a commercially available multiprocessor.<<ETX>>
ieee international symposium on fault tolerant computing | 1998
Ram Chillarege; Robert W. Horst; Clifford B. Meltzer; Angelo Pruscino; Dalibor F. Vrsalovic
High availability is critical to the future of the information technology (IT) business. In many ways, it is fundamental to the future of the world economy as we become more reliant on the global infrastructure, Today it is not uncommon to witness losses exceeding /spl epsi/ per hour of outage in many segments of the industry. What is alarming is that there is no articulated vision on how high availability is to be achieved for end-to-end solutions running on the current global infrastructure. The goal of the Industrial Council is to develop a vision for high availability which can cut across many industries.
hawaii international conference on system sciences | 1991
Nino Vidovic; Dalibor F. Vrsalovic; Leo Budin
The parallel computational model with data flow sequencing is introduced. Description of the basic principles and features of mpDF, a massively parallel architecture, based on the dataflow operational model and RISC organizational principles is presented. The analytical performance model is developed to evaluate proposed architectural solution for distributed/parallel computing based on data flow sequencing of instructions. Algorithmic performance model is extended to include characterization of the parallel programs in terms of the average parallelism. Model is solved for number of different workloads. The values of the basic architectural characteristics are analyzed showing that architecture is well balanced providing consistent performance made for wide rage of parallel applications.<<ETX>>
international symposium on computer architecture | 1985
Dalibor F. Vrsalovic; Edward F. Gehringer; Zary Segall; Daniel P. Siewiorek