Damena D. Agonafer

Low Reynolds number flow across an array of cylindrical microposts in a microchannel and figure-of-merit analysis of micropost-filled microreactors

Micropost-filled reactors are commonly found in many micro-total analysis system applications because of their large surface area for the surrounding volume. Design rules for micropost-filled reactors are presented here to optimize the performance of a micro-preconcentrator, which is a component of a micro-gas chromatography system. A key figure of merit for the performance of the micropost-filled preconcentrator is to minimize the pressure drop while maximizing the surface-area-to-volume ratio for a given overall channel geometry. Several independent models from the literature are used to predict the flow resistance across the micropost-filled channels for low Reynolds number flows. The pressure drop can be expressed solely as a function of a couple of design parameters: β = a/s, the ratio of the radius of each post to the half-spacing between two adjacent posts, and N, the number of microposts in a row. Pressure drop measurements are performed to experimentally corroborate the flow resistance models and the optimization scheme using the figure of merit. As the number of microposts for a given β increases in a given channel size, a greater surface-area-to-volume ratio will result for a fixed pressure drop. Therefore, increasing the arrays of posts with smaller diameters and spacing will optimize the microreactor for larger surface area for a given flow resistance, at least until Knudsen flow begins to dominate.

Cooling Limits for GaN HEMT Technology

The peak power density of GaN HEMT technology is limited by a hierarchy of thermal resistances from the junction to the ambient. Here we explore the ultimate or fundamental cooling limits made possible by advanced thermal management technologies including GaN-diamond composites and nanoengineered heat sinks. Through continued attention to near-junction resistances and extreme flux convection, power densities that may exceed 50 kW/cm2 - depending on gate width and hotspot dimension - are feasible within 5 years.

Thermal management of die stacking architecture that includes memory and logic processor

The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit (IC) packaging requirements. Previously, present authors reported on the thermal challenges of various die stacking architectures that included memory (volatile and non-volatile) only. In this paper, the focus is on stacking memory and the logic processor on the same substrate. In present technologies, logic processor and memory packages are located side-by-side on the board or they are packaged separately and then stacked on top of each other (package-on-package [PoP]). Mixing memory and logic processor in the same stack has advantage and challenges, but requires the integration ability of economies-of-scale. Geometries needed were generated by using Pro/Engineerreg Wildfiretrade 2.0 as a computer-aided-design (CAD) tool and were transferred to ANSYSreg Workbenchtrade10.0, where meshed analysis was conducted. Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant. The values of these parameters were determined to give a junction temperature of 100degC, which is an unacceptable value due to wafer level electromigration. A discussion is presented in what parameters need to be adjusted in order to meet the required thermal design specification. In that light, a list of solutions consisting of increasing the heat transfer co-efficient on top of the package, the use of underfill, improved thermal conductivity of the PCB, and the use of a copper heat spreader were evaluated. Results were evaluated in the light of market segment requirements

Inverse opals for fluid delivery in electronics cooling systems

We report the fabrication and fluid flow characterization of a class of open-cell copper foams known as copper inverse opals (CIOs). This material has finely controlled structure at the pore level, which may enable its use in microscale heat exchangers for microelectronics cooling. We fabricated CIOs by electrodepositing copper around a sacrificial template of packed polystyrene microspheres. We then removed the CIOs from their substrates and used electroetching to vary the pore structure and porosity. We characterized the geometry of the samples at various stages of fabrication with visual inspection and image analysis of scanning electron micrographs. We characterized the permeability with a through-plane flow rig and developed computational models for fluid flow in ideal face-centered cubic and hexagonally close-packed unit cells. Here we report the simulated and experimentally measured values of permeability. We also report experimental challenges that arise from the microscale dimensions of the samples.

High heat flux two-phase cooling of electronics with integrated diamond/porous copper heat sinks and microfluidic coolant supply

We here present an approach to cooling of electronics requiring dissipation of extreme heat fluxes exceeding 1 kW/cm2 over ~1 cm2 areas. The approach applies a combination of heat spreading using laser micromachined diamond heat sinks; evaporation/boiling in fine featured (5 μm) conformal porous copper coatings; microfluidic liquid routing for uniform coolant supply over the surface of the heat sink; and phase separation to control distribution of liquid and vapor phases. We characterize the performance of these technologies independently and integrated into functional devices. We report two-phase heat transfer performance of diamond/porous copper heat sinks with microfluidic manifolding at full device scales (0.7 cm2) with heat fluxes exceeding 1300 W/cm2 using water working fluid. We further show application of hydrophobic phase separation membranes for phase management with heat dissipation exceeding 450 W/cm2 at the scale of a single extended surface (~300 μm).

Three-Dimensional CFD Model of Pressure Drop in µTAS Devices in a Microchannel

Microposts are utilized to enhance heat transfer, adsorption/desorption, and surface chemical reactions. In a previous study [Yeom , J. Micromech. Microeng., 19, p. 065025 (2009)], based in part on an experimental study, an analytical expression was developed to predict the pressure drop across a microchannel filled with arrays of posts with the goal of fabricating more efficient micro-total analysis systems (µTAS) devices for a given pumping power. In particular, a key figure of merit for the design of micropost-filled reactors, based on the flow resistance models was reported thus providing engineers with a design rule to develop efficient µTAS devices. The study did not include the effects of the walls bounding the microposts. In this paper, a three-dimensional computational fluid dynamics model is used to include the effects of three-dimensionality brought about by the walls of the µTAS devices that bound the microposted structures. In addition, posts of smaller size that could not be fabricated for the experiments were also included. It is found that the two- and three-dimensional effects depend on values of the aspect ratio and the blockage ratios. The Reynolds number considered in the experiment that ranged from 1 to 10 was extended to 300 to help determine the range of Re for which the FOM model is applicable.

Progress on Phase Separation Microfluidics

High power density GaN HEMT technology can increase the capability of defense electronics systems with the reduction of CSWaP. However, thermal limitations have currently limited the inherent capabilities of this technology where transistor-level power densities that exceed 10 kW/cm2 are electrically feasible. This paper introduces the concept of an evaporative microcooling device utilizing some of the current two-phase vapor separation technologies currently being developed for water and dielectric liquids.

Surface Characterization Studies of Thiols as a Blocking Mechanism for Specific Adsorption for Application of Charge Selective Membrane Transport

This paper proposes the use of electrochemical impedance spectroscopy (EIS) to measure characteristics of gold (Au)-coated membranes and their inherent limitations. In this work, the fabrication of a membrane permeate flow cell is described with the aim of subsequently studying the transport of ions through conductive polycarbonate track etched membrane (PCTE) by interrogating the system using EIS and CV measurements. In particular, we would like to ascertain the voltage range that can be applied to the Au-coated membrane without getting a considerable faradaic activity; the difference between platinum and Au electrode; the effects of different electrolyte concentrations and various applied DC potentials.We extend our previous work done [1] by studying the differences of using a hrydroxyl and methyl terminated self assembled monolayer (SAM). We also extend the quality of the monolayer with respect to the amount of time in which the monolayer is grown. Finally, finding the voltage in which a ‘defect free’ monolayer transforms from insulative to ‘leaky’ behavior extends a detailed analysis of the critical voltage of an alkane thiol.Copyright

Study of Alkane Thiols as a Blocking Mechanism for Specific Adsorption for Application of Charge Selective Membrane Transport

Electrodialysis (ED) is an electrochemical process used for separation of ions across perm-selective membranes. ED uses a DC bias to selectively transport ions across membranes for applications ranging from desalination of water to demineralization of fruit juice. The energy cost of ED is due to accumulation of hydroxide and hydronium ions from the electrochemical process of water; additionally there is the cost of using platinum electrodes. This paper addresses the idea of using polycarbonate track etched membrane (PCTE) coated with gold between the membranes to reduce the energy cost and to explore a wider selection of electrode materials. This paper aims to show how thiol monolayers on gold can be used as ideal polarizable electrodes (electrode behaves like a capacitor with only charging current and no faradaic current) for application of potential to the membrane surface double layer. We report the characterization of such monolayers on gold-coated microscope slides. The goal is to control the diffuse layer potential at each membrane-solution interface while at the same time prevent adsorption on the electrode surface and minimize Faradaic activity due to electrolyte and redox species in solution. This lays the groundwork for the application of thiol-modified polycarbonate track-etched membranes for ion-selective transport. The paper proposes the use of electrochemical impedance spectroscopy (EIS) to measure characteristics of gold (Au)-coated membranes and their inherent limitations. In this work, the fabrication of a membrane permeate flow cell is described with the aim of subsequently studying the transport of ions through conductive polycarbonate track etched membrane (PCTE) by interrogating the system using EIS and CV measurements. In particular, we would like to ascertain the voltage range that can be applied to the Au-coated membrane without getting a considerable faradaic activity; the difference between platinum and Au electrode; the effects of different electrolyte concentrations and various applied DC potentials.Copyright

Aerogel for Microsystems Thermal Insulation: System Design and Process Development

Extreme miniaturization in the microelectronics component market along with the emergence of system-on-chip applications has driven interest in correspondingly small-scale thermal management designs requiring novel material systems. This paper concentrates on aerogel, which is an amorphous, nanoporous dielectric oxide fabricated through a sol-gel process. Its extremely high porosity leads to very low thermal conductivity and dielectric constants. Significant research has been devoted to its electrical properties; however, there are several emerging applications that can leverage the thermal characteristics as well. Two promising applications are investigated in this paper: a monolithically integrated infrared sensor that requires thermal isolation between sensor and silicon substrate, and an ultra-miniature crystal oscillator device which demands thermal insulation of the crystal for low-power operation. This paper identifies the potential benefits of aerogel in these applications through system modeling, demonstrates aerogel’s compatibility with standard low-cost microfabrication techniques, and presents results of thermal testing of aerogel films compared with other microelectronics insulators and available data in the literature. The goal is to explore system thermal design using aerogel while demonstrating its feasibility through experimentation. The combination of numerical simulations, Bayesian surrogate modeling, and process development helps to refine candidate aerogel applications and allow the designer to explore thermal designs which have not previously been possible in large-scale microelectronics system production. This paper was also originally published as part of the Proceedings of the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems.© 2005 ASME