Mehdi Asheghi

Thermal conduction in ultrathin pure and doped single-crystal silicon layers at high temperatures

This work presents the in-plane thermal-conductivity data for pure as well as boron-doped (1.6×1021∕cm3), arsenic-doped (2.3×1020∕cm3), and phosphorus-doped (2.3×1020∕cm3) silicon layers of thickness 30nm in the temperature range of 300–450K. The steady-state Joule heating and electrical resistance thermometry are used to measure the lateral thermal conductivity of suspended silicon layers. Thermal-conductivity data for pure and doped single-crystalline thin silicon layers can be interpreted using thermal-conductivity integral in relaxation-time approximation that accounts for phonon-boundary and phonon-impurity scatterings. No additional fitting parameters are used in this work in contrast with previous studies that required an unusually large phonon-impurity scattering coefficient to fit the thermal-conductivity data for bulk doped silicon to the predictions of the thermal-conductivity integral in relaxation-time approximation.

Efficient full-chip thermal modeling and analysis

The ever-increasing power consumption and packaging density of integrated systems creates on-chip temperatures and gradients that can have a substantial impact on performance and reliability. While it is conceptually understood that a thermal equivalent circuit can be constructed to characterize the temperature gradients across the chip, direct and iterative solutions of the corresponding 3D equations are often intractable for a full-chip analysis. Multigrid accelerated iterative methods can be applied to solve the equivalent circuit problem that is provably symmetric positive definite; however, explicitly building the matrix problem is intractable for most full-chip problems. In This work we present a multigrid iterative approach for the full-chip thermal analysis which does not require explicit construction of the equivalent circuit matrix. We propose specific multigrid treatments to cope with the strong anisotropy of the full-chip thermal problem that is created by the vast difference in material thermal properties and chip geometries. Importantly, we demonstrate that only with careful thermal modeling assumptions and appropriate choices for grid hierarchy, multigrid operators and smoothing steps across grid points, can we accurately and efficiently analyze a full-chip thermal problem. Experimental results demonstrate the efficacy of the proposed multigrid methodology. Our prototyped thermal simulator is able to solve a steady-state problem with more than 10 million unknowns in 125 CPU seconds with a peak memory usage of 231 mega bytes.

Phase change random access memory, thermal analysis

Despite very encouraging progress in recent years, phase change random access memory (ovonic unified memory, OUM) still faces several problems, such as reliability (lifetime), power consumption and speed, which need to be resolved before it can be commercialized. There have been a number of attempts to address such problems, even through devising other alternatives such as line memory and thermal GST memory cells. However, a comprehensive thermal engineering of the OUM memory cell is missing from the literature, and yet can have a great impact on design and optimization of the device. Such an analysis can definitely serve the OUM technology to achieve the optimum design and can even be used as a guideline for defining the research path. This manuscript provides an insight into the thermal issues and phenomena in the phase change random access memory cell. I-structure is proposed for OUM which has the combined features of T-structure and the line memory cell

Impact of Power Granularity On Chip Thermal Modeling

In this paper we investigate the impact of the granularity of the power distribution for accurately predicting semiconductor chip temperature fields. Specifically, we calculate the transfer functions between power distributions and resulting temperature maps for various microprocessor packages and cooling conditions, which establish a minimum granularity required for accurate thermal analysis. The purpose of this paper is twofold: first, we like to provide some general guidelines for the impact of different power granularities on the global chip temperatures and second we intend to spike a broader discussion about to which extent small heating effects can affect chip temperatures for circuits under full operation. As such this work is not only beneficial for package and cooling solution engineering but also important to circuit designers and computer architects in their battle against hotspots in microprocessors

Thermal and electrical characterization of Cu/CoFe superlattices

The present work is directed at thermal and electrical characterization of the Cu/CoFe multilayer, which is made of extremely thin periodic layers, using steady-state Joule heating and thermometry in suspended bridges in the temperature range of 50–300 K. The total thickness of the layer is ds=144u2002nm, while the thickness of individual repeats are 12 and 21 A for CoFe and Cu layers, respectively. The experimental data for thermal conductivity of a 144-nm-thick single Cu layer is also presented for comparison. The experimental data indicates that the spin-dependent electron scattering at the Cu/CoFe interface contributes to a strong reduction in thermal conductivity of these layers compared to the bulk values. The calculated Lorenz numbers (from the thermal and electrical conductivity data) varies by nearly a factor 2 from 4×10−8u2002Wu200aΩu200aK−2 at 50 K to 1.8×10−8u2002Wu200aΩu200aK−2 at 300 K and is different from the free electron value of L0=2.45×10−8u2002Wu200aΩu200aK−2. This implies that the Wiedemann-Franz law does not hold for Cu/C...

Thermal characterization of thin film Cu interconnects for the next generation of microelectronic devices

With the dramatic scaling of the transistors, the important issues like RC delay, electromigration failure and heat dissipation emerge, which need to be addressed urgently. Substitution of copper for aluminum has been suggested to reduce the RC delay of interconnects. While the electrical and mechanical properties of thin copper films have been extensively investigated; their thermal characterizations have received less attention. The lateral thermal conductivity of a 144 nm thick copper film is measured using the electrical resistance Joule heating and thermometry in a suspended bridge. The thermal conductivities at 300 K and 450 K are 240 and 280 W/m-K, respectively, which is smaller than the corresponding bulk values. The impact of the interconnect dimension and thermal conductivity on the self-heating is investigated as a function of interconnect via density. It is concluded that for via separation distances less than 5 /spl mu/m, the combination of Cu interconnect and vias can significantly reduce the average temperature rise in multilayer interconnects.

Field-dependent thermal and electrical transports in Cu∕CoFe multilayer

This paper reports field-dependent thermal and electrical conductivity measurements of a 144 nm thick Cu∕CoFe giant magnetoresistive multilayer made of extremely thin periodic layers (12 and 21 A for CoFe and Cu layers, respectively), using steady-state Joule heating and electrical resistance thermometry in suspended bridges between 300 and 380 K. Large decreases in the electrical and thermal resistivities from antiparallel to parallel alignment of the magnetization in the film, referred to as the giant magnetoresistance (GMR) and giant magnetothermal resistance (GMTR), are observed. GMR ratios of 17% and 12% and large GMTR ratios of 25% and 58% are measured at 300 and 380 K, respectively. It is concluded that different electron scattering rates for charge and heat transports in the ferromagnetic CoFe layer are responsible for the difference between the GMR and GMTR ratios. While the previous works only reported the relative change in thermal conductance due to applied magnetic field, the present manuscri...

Thermal characterization of dielectric and phase change materials for the optical recording applications

Advances in the phase change optical recording technology strongly depend on the optical and thermal optimizations of the metal/ZnS–SiO2/phase change multilayer structure, which requires accurate modeling and thermal characterization of the phase change media structure. In the present work, the thermal conductivities of the amorphous and crystalline Ge4Sb1Te5 phase change and ZnS–SiO2 dielectric layers of thicknesses in the range of 50–300nm have been measured using the transient thermoreflectance technique. The data are between factors of 2–4 different from the previously measured values for thin film and bulk samples. The thermal boundary resistance at a metal/ZnS–SiO2 interface is found to be around 7×10−8m2W−1. This might have serious implications for the future phase change recording application which attempts to achieve the high writing speeds by decreasing the thickness of a ZnS–SiO2 dielectric layer.

Thermal modeling of self-heating in strained-silicon MOSFETs

Self-heating is a pressing issue for both the silicon-on-insulator (SOI) and Strained-Si technologies, where the devices are separated from the silicon substrate by poor thermal conducting layers. Although seemingly counterintuitive, the level of self-heating in a strained-Si transistor could be comparable with that of the SOI device due to the poor thermal conductivity of the thick Si/sub 0.8/Ge/sub 0.2/ underlayer (/spl sim/5 W/m-K). The lateral thermal conduction in strained-Si layer of thickness near 10-20 nm would somewhat reduce the maximum temperature rise in the device but is significantly reduced due to the phonon-boundary scattering. In the absence of effective tools for sub-continuum heat transfer modeling, reduced thermal conductivity values for thin silicon and Si/Si/sub 0.8/Ge/sub 0.2/ are used in a one-dimensional multi-fin model that accounts for the lateral conduction in the channel, source and drain as well as heat loss to the Si/sub 0.8/Ge/sub 0.2/ underlayer. This provides a simple yet effective tool for thermal simulations of the strained-Si transistors, which can also be extended to the SiGe-on-insulator (SGOI) technology.

Modeling of Localized Heating Effect in Sub-Micron Silicon Transistors

The performance and reliability of sub-micron semiconductor transistors demands accurate modeling of electron and phonon transport at nanoscales. The continued downscaling of the critical dimensions, introduces hotspots, inside transistors, with dimensions much smaller than phonon mean free path. This phenomenon, known as localized heating effect, results in a relatively high temperature at the hotspot that cannot be predicted using heat diffusion equation. While the contribution of the localized heating effect to the total device thermal resistance is significant during the normal operation of transistors, it has even greater implications for the thermoelectrical behavior of the device during an electrostatic discharge (ESD) event. The Boltzmann transport equation (BTE) can be used to capture the ballistic phonon transport in the vicinity of a hot spot but many of the existing solutions are limited to the one-dimensional and simple geometry configurations. We report our initial progress in solving the two dimensional Boltzmann transport equation for a hot spot in an infinite media (silicon) with constant temperature boundary condition and uniform heat generation configuration.Copyright