Damian A. Morero

Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks

This paper presents a non-concatenated forward error correction (FEC) code suitable for applications in 100Gb/s optical transport networks (OTN). A typical requirement in this application is a net coding gain (NCG) >10 dB at a bit error rate (BER) of 10^{-15} with an overhead (OH) of ~20%. As discussed in [1], non-concatenated codes are the ultimate frontier in terms of performance for OTN applications, because of their superior performance, lower latency, and lower overhead than concatenated codes. However, a major stumbling block for the use of these codes has been the existence of BER floors at levels significantly higher than the required 10^{-15} (typically 10^{- 10}). In this paper we present a new coding scheme based on a low density parity check (LDPC) code with an expected net coding gain of 11.30dB at 10^{-15}, 20% OH, and a block size of 24576 bits. This represents a significant improvement over the previous state of the art [2], based on a concatenated code with a block size of 74844 bits and 20.5% OH. The code is designed to minimize the BER floor while simultaneously reducing the memory requirements and the interconnection complexity of the iterative decoder [3]. Experimental results obtained with an FPGA-based hardware emulator demonstrate an NCG of 10.70 dB at a BER of 10^{-13} and no error floors. These experimental results are extrapolated to 10^{-15} using importance sampling techniques, resulting in the expected performance stated above. Moreover, we find that fixed-point implementation is the main cause of error floors below 10^{-13}. Based on this finding, we introduce a new low complexity postprocessing technique to push BER floors down to 10^{-15}.

Design Tradeoffs and Challenges in Practical Coherent Optical Transceiver Implementations

This tutorial discusses the design and ASIC implementation of coherent optical transceivers. Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are presented. Particular emphasis is placed on flexible (or reconfigurable) transceivers because of their importance as building blocks of software-defined optical networks. The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations. Complexity and performance of critical DSP blocks such as the forward error correction decoder and the frequency-domain bulk chromatic dispersion equalizer are analyzed in detail. Other important ASIC implementation aspects including physical design, signal and power integrity, and design for testability, are also discussed.

Novel serial code concatenation strategies for error floor mitigation of low-density parity-check and turbo product codes

This paper presents a novel multiple serial code concatenation (SCC) strategy to combat the error-floor problem in iterated sparse graph-based error correcting codes such as turbo product-codes (TPC) and low-density parity-check (LDPC) codes. Although SCC has been widely used in the past to reduce the error-floor in iterative decoders, the main stumbling block for its practical application in high-speed communication systems has been the need for long and complex outer codes. Alternative, short outer block codes with interleaving have been shown to provide a good tradeoff between complexity and performance. Nevertheless, their application to next-generation high-speed communication systems is still a major challenge as a result of the careful design of long complex interleavers needed to meet the requirements of these applications. The SCC scheme proposed in this work is based on the use of short outer block codes. Departing from techniques used in previous proposals, the long outer code and interleaver are replaced by a simple block code combined with a novel encoding/decoding strategy. This allows the proposed SCC to provide a better tradeoff between performance and complexity than previous techniques. Several application examples showing the benefits of the proposed SCC are described. Particularly, a new coding scheme suitable for high-speed optical communication is introduced.

FPGA implementation of the parity check node for min-sum LDPC decoders

A typical high-speed decoder implementation for an LDPC may require hundreds or even thousands of variable and check node processors. Since check node processing unit (CNPU) is far more complex than variable processing unit, hardware requirements of CNPU has a big impact on the final decoder complexity. Here, an FPGA implementation of the soft parity check node for min-sum LDPC decoders is analyzed. The hardware cost and speed of the main block of CNPU, which finds the two smallest input values, is thoroughly studied for different numbers of input values with different bit-widths. Experiments for an FPGA implementation demonstrate that hardware cost and speed vary with the number of input values in the same way as they do for an ASIC implementation. Furthermore, it is shown that more than 60% of the hardware resources of the CNPU is used for finding the two smallest input values.

Efficient concatenated coding schemes for error floor reduction of LDPC and turbo product codes

This work introduces a novel serial code concatenation (SCC) scheme to combat the error floor problem experienced in iterated sparse graph-based error correcting codes such as turbo product (TP) codes and low density parity check (LDPC) codes. SCC has been widely used in the past to reduce the error floor in iterative decoders. However, the main stumbling block for its practical application in high speed communication systems has been the need for long and complex outer codes. The use of short outer block codes with interleaving has been shown to provide a good tradeoff between complexity and performance. Nevertheless, its application to next-generation ultra high-speed communication systems is still a major challenge as a result of the careful design of long complex interleavers needed to meet the requirements of these applications (e.g., a net coding gain >10 dB at a bit error rate of 10−15 with an overhead of ∼ 20% for 100 Gb/s optical transport networks [1]). In this paper we present a new SCC scheme built from short outer block codes. Unlike previous proposals, the long interleaver is replaced by a simple block code combined with a novel encoding/decoding strategy. Based on this finding, we show that complexity and latency can be drastically reduced with negligible penalty. The SCC technique introduced here provides a new general framework for solving the error floor problem induced by low-weight error patterns of any coding scheme.

Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems

Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for optimization and performance evaluation of LDPC codes. The proposed FPGA framework includes several features such as the capability of changing the internal resolution of the decoder algorithm or capturing error patterns for error-floor analysis. Experimental results derived from the FPGA platform show that the designed QC-LDPC code is able to achieve an NCG of 11.6 dB at a bit-error-rate (BER) of 10−15 with an overhead of 25% and a codeword length of only 16K bits.

Performance of Euclidean-Metric MLSD Receiver in the Presence of Channel Mismatch Caused by Nongaussian Noise

In this paper we present a theory of the bit error rate (BER) of Euclidean metric-based maximum likelihood sequence detectors (EM-MLSD) in the presence of channel mismatch caused by nongaussian noise. Although the theory is general, here we focus on the effects of quantization noise (QN) added by the front-end analog-to-digital converter (ADC) typically used in DSP based implementations of the receiver. Numerical results show a close agreement between the predictions of the theoretical analysis and computer simulations. As a practical application of the proposed theory, we investigate the performance of EM-MLSD in 10Gb/s Ethernet receivers for multimode optical fibers. Since the BER required in this application is below 10^-12, which precludes the use of computer simulations to estimate BER, a theoretical study of the MLSD performance including the combined effects of the channel dispersion and QN, becomes necessary. We present numerical results for the three stressors specified by the 10GBASE-LRM standard. Our study shows that the impact of the QN added by the ADC on the performance depends strongly on the channel dispersion (i.e., the stressor).