Graciela Corral-Briones

Capacity of Generalized UTRA FDD Closed-Loop Transmit Diversity Modes

Transmit diversity techniques have received a lot of attention recently, and open-loop and closed-loop downlink transmit diversity modes for two transmit antennae have been included into universal terrestrial radio access (UTRA) frequency division duplex (FDD) specification. Closed-loop modes provide larger system capacity than open-loop modes, but they need additional side information of the downlink channel in the transmitter. In FDD systems this requires a separate feedback channel. Quantization of channel state information (CSI) in closed-loop transmit diversity schemes decreases the performance when compared to a closed-loop system where the transmitter has access to complete CSI. In this paper, we analyze the effect of quantization of CSI and deduce approximate capacity formulae for closed-loop transmit diversity schemes that are generalizations of the closed-loop schemes included in UTRA FDD specification. Moreover, we calculate approximation error and show by simulations that our approximation is tight for flat Rayleigh fading environments with and without fast transmit power control.

On throughput-fairness tradeoff in virtual MIMO systems with limited feedback

We investigate the performance of channel-aware scheduling algorithms designed for the downlink of a wireless communication system. Our study focuses on a two-transmit antenna cellular system, where the base station can only rely on quantized versions of channel state information to carry out scheduling decisions. The motivation is to study the interaction between throughput and fairness of practical spatial multiplexing schemes when implemented using existing physical layer signaling, such as the one that exists in current wideband code division multiple access downlink. Virtual MIMO system selects at each time instant a pair of users that report orthogonal (quantized) channels. Closed-form expressions for the achievable sum-rate of three different channel-aware scheduling rules are presented using an analytical framework that is derived in this work. Our analysis reveals that simple scheduling procedures allow to reap a large fraction (in the order of 80%) of the sum-rate performance that greedy scheduling provides. This overall throughput performance is obtained without affecting considerably the optimal short-term fairness behavior that the end users would perceive.

A New Parallel Carrier Recovery Architecture for Intradyne Coherent Optical Receivers in the Presence of Laser Frequency Fluctuations

This paper introduces a new parallel carrier recovery architecture suitable for ultra- high speed intradyne coherent optical receivers (e.g., >=40Gb/s). The proposed scheme combines a novel low-latency parallel digital phase locked loop (DPLL) with a feedforward carrier phase recovery (CPR) algorithm. The new low-latency parallel DPLL is designed to compensate not only frequency offset, but also frequency fluctuations such as those induced by mechanical vibrations. It is well-known that nonzero frequency offset leads to higher phase error variance in a feedforward CPR [1]. Furthermore, it has been recently shown that laser frequency instability caused by mechanical vibrations significantly degrades the performance of CPR [2]. Other effects such as power supply noise may also introduce laser frequency fluctuations. To avoid receiver performance degradations, both frequency offset and frequency fluctuations should be compensated before the feedforward CPR block. We show that this task can be achieved by using a typical decision-directed serial DPLL. Then, a new approximation to the DPLL computation is introduced to enable a parallel-processing implementation in multigigabit per second receivers. The proposed technique reduces the latency within the feedback loop of the DPLL introduced by parallel processing, while providing a bandwidth and capture range close to those achieved by a serial DPLL. Simulation results demonstrate that the effects caused by frequency deviations can be eliminated with the proposed parallel carrier recovery architecture.

Downlink multiuser scheduling algorithms with HSDPA closed-loop feedback information

System capacity can be increased if the base station (BS) is equipped with additional channel state information (CSI) of the downlink channel. In an FDD system, this means that mobiles have to provide CSI through some feedback mechanism. Although the two feedback modes included in the present WCDMA HSDPA standard have been designed for one-by-one transmission, a significant downlink throughput improvement can be achieved with multiuser scheduling (MS) [A. Dowhuszko et al., 2005]. In this paper we propose two practical MS algorithms compatible with the current HSDPA specification, that provide a significant performance gain at moderate power regimes, compared to the systems that transmit sequentially to the user with best channel.

MMSEC-RAKE receivers with resolution reduction of the diversity branches: analysis, simulation, and applications

In channels where the delay spread is smaller than the chip interval (e.g., an IS-95 system operating in indoor environments), spread-spectrum signals do not give rise to path diversity. In this situation, maximal-ratio combiner (MRC) RAKE receivers with resolution reduction (RR) of the diversity receiver branches may be used by the mobile stations to provide diversity gain, significantly improving system performance. A new resolution reduction technique based on the use of a minimum mean-square-error diversity combiner (MMSEC) is proposed in this work. We show that, under very general assumptions, this new method of RR is optimal. A detailed study of the performance of a dual-branch MMSEC-RAKE receiver with RR in a typical indoor office environment is presented. In order to allow a simple practical implementation, a suboptimal structure of the MMSEC is also proposed. Numerical results show that this new receiver scheme provides a 1.2-dB improvement over the previously proposed RR technique based on MRC, and a 4.9-dB improvement over conventional MRC-RAKE receiver without RR, at a frame-error rate of 0.01 for the downlink of the IS-95 system in a typical indoor office environment.

Achievable Sum-Rate Analysis of Practical Multiuser Scheduling Schemes with Limited Feedback

We study the performance of fair physical layer schedulers that select a pair of orthogonal users for simultaneous transmission. The schemes rely on partial channel state information compatible with 3GPP specifications and differ with respect to their usage of channel quality indicator in scheduling decisions. Closed-form expressions for the achievable sum-rate of three practical scheduling algorithms are derived.

Achievable data rates for two transmit antenna broadcast channels with WCDMA HSDPA feedback information

Previous works have shown that in case of multiple transmit antenna broadcast channels, the total system throughput can be greatly improved by combining spatial prefiltering (SP) with multiuser scheduling (MS) [G. Caire et al., 2003], [D. Samardzija et al., 2003]. However, most of the studies assume full channel state information at the transmitter (CSIT). In this paper, we study the achievable data rates within the current WCDMA HSDPA specification and present different schemes based on the WCDMA closed-loop transmit diversity (CLTD) modes. Although the achievable throughput is interference limited at high SNR due to partial CSIT, we show that at moderate power regimes a significant performance gain can be achieved by the proper combination of SP and MS concepts, compared to the systems that only transmit to the user with the best channel condition in each transmission time interval (TTI).

Compensation of Laser Frequency Fluctuations and Phase Noise in 16-QAM Coherent Receivers

Frequency fluctuations caused by mechanical vibrations, power supply noise, and other mechanisms are detrimental to the phase estimator performance in high speed intradyne coherent optical receivers. In this letter, we propose the use of a low-latency parallel digital phase lock loop in combination with common feed-forward carrier phase recovery algorithms in order to compensate both the phase noise and laser frequency fluctuation effects on 16-quadrature amplitude modulation receivers. Numerical results demonstrate the excellent behavior of the proposed two-stage carrier recovery scheme.

Reduced complexity multiuser receivers for asynchronous trellis coded DS-CDMA systems

Previous works have shown that multiuser receivers with trellis-coded modulation significantly improve performance in CDMA transmissions over bandwidth limited AWGN channels. In Corral-Briones et al., a reduced-state multiuser receiver (RSMR) that jointly decodes the trellis code and equalizes the multiuser interference of the channel has been introduced. In this paper the performance of this reduced-state family is studied for a heavily loaded bandwidth limited communication system. Unlike the previous work we address the performance of RSMR in situations of practical interest such as in high bandwidth efficiency situations and in near-far situations. Simulation results show that performance near the trellis-coded single user bound is achieved with this scheme at a drastically reduced complexity compared with that of the optimal receiver. Moreover we analyze the near-far resistance of RSMR and other suboptimal schemes. Results show that RSMR significantly outperforms previously known suboptimal structures.

A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems

This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.