Damir Ferenci

Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS

A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2mm2 while the ADC core area is 0.16mm2.

A 28GS/s 6b pseudo segmented current steering DAC in 90nm CMOS

A pseudo segmented twofold time-interleaved 6-bit digital-to-analog converter (DAC) occupies 0.28 mm2 chip area in a standard 90 nm CMOS technology. The DAC enables sampling rates up to 28 GS/s with a power consumption of 2.25 W at a −2.5 V power supply. The output bandwidth is at least 14 GHz. The integral non-linearity (INL) and the differential non-linearity (DNL) are 0.8 LSB and 1 LSB respectively. The estimated effective number of bit (ENOB) at 25 GS/s are 5.5-bit at DC and 4.6-bit at the Nyquist frequency.

A 25 GHz Analog Multiplexer for a 50GS/s D/A-Conversion System in InP DHBT Technology

An analog 2:1 multiplexer for high speed analog multiplexing is presented in InP DHBT technology. The multiplexer features a SNDR above 26 dB with a differential input voltage of 1V-PP and a 3 dB corner frequency above 40GHz. The power consumption of the multiplexer is 1.35W at a supply voltage of 5.5V. The multiplexer is suitable for the realization of a 50GS/s digital-to-analog conversion system, which is more than two times faster than currently available fully sampling rate flexible D/A-conversion systems.

A 25 GHz analog demultiplexer with a novel track and hold circuit for a 50 GS/s A/D-conversion system in InP DHBT Technology

A novel architecture of a track and hold (T&H) circuit for the realization of a high speed analog demultiplexer is presented in InP DHBT Technology. The architecture allows a sampling rate flexible demultiplexing of an analog input signal. The demultiplexer features a measured THD above 32 dB and a SFDR above 35 dB with a differential input voltage of 0.5V-PP when operating at 25 GHz. This allows the realization of a 50 GS/s analog-to-digital conversion system.

Design of a quadrature clock conditioning circuit in 90-nm CMOS technology

This paper presents the operation and problems of the conventional clock conditioning circuits. A modified design is proposed to eliminate these problems and to merge two conditioning circuits together. This is to adjust and maintain two output signal properties actively during circuit operation for 4-phase 10 GHz single-ended clock signals. It is desired to have an exact 50% duty-cycle for each signal and a 90° phase difference between them. Simulation results in 90-nm CMOS technology are provided showing low output jitter.

High-speed CMOS DACs and ADCs for broadband communication

High speed DACs and ADCs are key components for mm-wave communication systems that apply spectral efficient modulation formats to achieve date rates up to 100 Gbit/s. CMOS converters enable the integration with a mm-wave front-end and a high-throughput DSP on a low-cost system-on-chip. We present CMOS ADC and DAC prototypes with conversion rates up to 36 GS/s, resolutions between 3 and 6 bit and real-time digital interfaces that enable experimental lab setups with the DSP functions implemented on FPGAs.

An analog 1:16 demultiplexer for time-interleaved A/D-converters with a sampling rate of up to 64 GS/s

An analog current-based 1:16-demultiplexer with integrated sample-and-hold is presented. It is designed in a 28 nm CMOS technology and is the basis for a 16-fold time-interleaved ADC. It offers sampling rates up to 64 GS/s, while consuming only 0.9 W of power and 2.6 mm2 of chip area.

A high speed linear buffer for A/D conversion beyond 100 GS/s in InP DHBT Technology

A linear buffer for high speed demultiplexing is presented in InP DHBT Technology. The buffer has a SNDR of 38 dB with a differential input voltage of 500mV-PP and a 3 dB corner frequency above 50 GHz. The power consumption of the buffer is 0.5W at a supply voltage of 5V. The buffer is suitable for applications which need a low amplification and a high output bandwidth e.g. in a high speed demultiplexer circuit.