Johannes Digel

IR-UWB single-chip transceiver for high-band operation compliant to IEEE 802.15.4a

This paper describes a monolithic integrated single-chip transceiver intended for impulse radio (IR) - Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6-bit-resolution successive approximation register (SAR) analogue-to-digital converter (ADC), and the baseband processor running with a clock of 31.2 MHz. The analogue frontend can be further segmented into a pulse generation and transmit part and a quadrature direct down conversion receiver part, whereas both parts share a frequency synthesizer based on an integer-N phase-locked loop (PLL). The impulse generation is based on the gated oscillator principle allowing required on-off keying (OOK) as well as binary phase shift keying (BPSK). While the receiver supports both, coherent and non-coherent impulse detection, here only non-coherent operation will be presented. The baseband processor part contains a separated 499.2 MHz clocked block for transmitter control and provides a serial peripheral interface (SPI) for data exchange with an external micro controller. The presented chip was fabricated in a 0.25 μm SiGe:C BiCMOS technology occupying a Si area of 3.25 - 3.25 mm2.

A 6 bit and a 7 bit 80 MS/s SAR ADC for an IR-UWB receiver

A 6 bit and a 7 bit successive approximation register (SAR) analog-to-digital converter (ADC) with conversion rates of up to 80 MS/s are presented in this paper. They will be used in an impulse-radio ultra-wideband (IR-UWB) receiver. The architecture with a switched-capacitor (SC) digital-to-analog converter (DAC) is applied due to its low power consumption. The 6 bit analog-to-digital converter applies the classic switching algorithm which is extended to 7 bit with a minor change to the analog part of the converter. A new kind of flip-flops is used in the SAR which enables synchronous operation during the conversion phase. The integrated circuit is realized in the 250 nm SiGe BiCMOS technology SGB25V of IHP. The cores of both analog-to-digital converters occupy a chip area of 0.36 × 0.28 mm2 and consume 5 mA from a 2.6 V supply.

A 6 GS/s 9.5 bit pipelined folding-interpolating ADC with 7.3 ENOB and 52.7 dBc SFDR in the 2nd Nyquist band in 0.25 µm SiGe-BiCMOS

A pipelined folding-interpolating ADC with a distributed quantizer is presented. The low-mismatch analog frontend provides for excellent SFDR and SNDR without calibration or digital post processing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves 7.3 ENOB and a SFDR of 52.7 dBc in the 2nd Nyquist band at 6 GS/s with an overall power consumption of 10.2 W.

Digital pulse-width pulse-position modulator in 28 nm CMOS for carrier frequencies up to 1 GHz

A fully digital pulse-width pulse-position modulator (D-PWPM) is proposed that is capable of providing pulse sequences for a switching-mode power amplifier. The pulse sequences are generated according to 6-bit digital input words defining the positions of the rising and falling edges without the need for tunable analog delay cells. All possible edge positions are derived by division and phase interpolation of a digital input clock signal that is a multiple of the carrier frequency. CMOS selectors provide two signals which carry the actual rising and falling edge positions to special symmetric CMOS NOR and NAND gates. They finally generate the modulated pulse sequence. The D-PWPM is fabricated in a 28 nm low-power CMOS technology and the circuit core dissipates 53mW from a 1 V supply. Sinusoidal double-sideband suppressed-carrier modulation of a 1 GHz carrier demonstrates the capability of the D-PWPM to operate as an RF bandpass mode DAC. With a carrier frequency of 983.04MHz, an SFDR of 45.6 dB is achieved for a low-frequency modulation and 33.4 dB near Nyquist frequency. Data transmission at 491.52MBit/s is demonstrated with a 16-QAM.

3-Path 5–6 GHz 0.25 μm SiGe BiCMOS power amplifier on thin substrate

This paper presents a fully integrated class-A mode Differential Power Amplifier (DPA) on a thin silicon substrate intended for being embedded into flexible electronic foil systems. A high-speed and cost-effective 95 GHz-fmax, 0.25 μm SiGe:C technology (IHP process SGB25V) is used. RF performance of DPA has been evaluated with the pre- and post-thinning measurement results at die level. The behavior of the PA has been optimized for 5–6 GHz frequency band and achieves 10.85 dB and 10 dB small-signal gain at 5.5 GHz before and after thinning, respectively. The measured large signal gain of amplifier at Pin 0 dBm is 10 dB before and 9.4 dB after thinning process. The simulated output referred 1 dB compression point is 10.76 dBm with a PAE of 15%. The PA consumes 50 mA under 1.5 V supply voltage. After thinning process, the supply current is lowered by 3 mA.

A 6-GS/s 9.5-b Single-Core Pipelined Folding-Interpolating ADC With 7.3 ENOB and 52.7-dBc SFDR in the Second Nyquist Band in 0.25-

A pipelined folding-interpolating analog-to-digital converter (ADC) with a distributed quantizer is presented. The mismatch-insensitive analog frontend provides excellent spurious-free dynamic range (SFDR) and signal-to-noise ratio without calibration or digital postprocessing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves an effective resolution of 7.3 b and an SFDR of 52.7 dBc in the second Nyquist band at 6 GS/s with an overall power consumption of 10.2 W.

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This paper presents a 10 bit 12.8 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 250 nm SiGe BiCMOS technology. An energy-efficient switching algorithm with top-plate sampling is applied which reduces the total input capacitance by 50%. High-impedance inputs with emitter followers and internal reference voltage generation make it suitable for applications that require precise on-chip voltage monitoring. For a low-frequency input signal, measured SNDR and SFDR of the presented SAR ADC are 48.7 dB and 57.8 dB. The effective resolution bandwidth (ERBW) is 19 MHz. The ADC draws 17.4 rnA from a 2.6 V supply including reference voltage generation, clock drivers and emitter follower buffers for input and reference voltages. The die area is 2.1 × 0.7 mm2 with the ADC core occupying 1 × 0.5 mm2. A formula for relating static nonlinearity (INL) measurements with dynamic SNDRIENOB measurements is derived. From output codes recorded with constant input voltages, the distortion power caused by nonlinearity and the noise of the reference voltage source and the comparator are determined. After adapting them to sinusoidal inputs, the expected impact on SNDR and ENOB is derived.

m SiGe-BiCMOS

An 15th order bandpass delta-sigma modulator for class-S power amplifiers is presented. The modulator is based on a third order low pass prototype which is designed to meet the requirements for signal-to-noise ratio (SNR) of major mobile communication standards in a bandwidth of around 30 MHz. The transform z⁻¹ → z⁻⁵ leads to a repetition of the low pass notch in the noise transfer function (NTF) at frequencies f = n/5f<inf>s</inf>, n = 1, 2, 3, 4, 5, &. Apart from sinc filtering due to rectangular output pulses the NTF shape is equal in all frequency bands. The two lower frequency bands at f = 1/5f<inf>s</inf>, 2/5 f<inf>s</inf> are independent from each other and can be used for concurrent transmission in the 450 MHz and 900 MHz band. The paper investigates the modulator with respect to the signal to noise ratio, the stability and the coding efficiency versus input amplitudes of tones in both frequency bands.