Damu Radhakrishnan

Low power CMOS pass logic 4-2 compressor for high-speed multiplication

A novel CMOS 4-2 compressor using pass logic is presented in this paper. An XOR-XNOR combination gate is used to build the circuit while totally eliminating the use of inverters. The total power dissipation has been cut down to a minimum while providing the full output voltage swing at all nodes in the circuit. Furthermore, the complete circuit is implemented with a bare minimum of 28 transistors.

Shift invert coding (SINV) for low power VLSI

Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transitions on the bus and bus invert coding is a widely popular technique for that. In this paper we introduce a new way of coding called the ShiftInv coding that is superior to the bus invert coding technique. Our simulation results show a considerable reduction on the number of transitions over and above that obtained with bus invert coding. Further, the proposed technique requires only 2 extra bits for the low power coding, regardless of the bit-width of the bus and does not assume anything about the nature of the data.

A new approach to data conversion: direct analog-to-residue converter

A novel design of a direct analog-to-residue converter is presented. The design makes use of two successive approximation analog-to-digital (A/D) converters, a few module adders and a small look-up table. One of the digital-to-analog converters is modified to generate outputs which are weighted by a constant factor, and one of the comparators is replaced by a difference amplifier. The look-up table needed is a very small percentage of the entire chip area and is shown to be only 840 bytes for a 36 bit residue number system converter.

Fast residue-to-binary converter architectures

Hardware efficient residue-to-binary converter architectures for three different moduli sets are presented in this paper. Two of them use three moduli each and the third one uses five moduli. One of the triple moduli sets has an extended dynamic range compared to the standard triple moduli set. In addition, the five moduli set covers a very large dynamic range.

Fault-tolerance scheme for an RNS MAC: performance and cost analysis

Residue number systems (RNS) are especially useful in applications in which fault-tolerance is a requirement. Accordingly, this paper discusses a novel and elegant fault-tolerance scheme incorporated into a multiply-accumulate (MAC) unit based on RNS. The fault-tolerance is achieved by using inexpensive forward conversion procedures. The cost and performance are analyzed with respect to other designs, and the analysis indicates superior cost:performance measure for our design.

A 36-bit balanced moduli MAC architecture

Recently a renewed interest is seen in RNS (Residue Number System) which stems out from the fact that these systems are inherently parallel and modular and thus are fast and simple. In many DSP applications Multiply-Accumulate (MAC) operation turns out to be the most basic one and hence an RNS based 36-bit MAC architecture is presented in this paper to speed up the whole operation. A further enhancement in speed up is achieved by exploiting the logarithmic properties of Galois fields and integer rings. The choice of forward and reverse converters used in the design results in considerable savings in silicon real estate. The adder cells used is based on pass transistor design which attribute to very low power consumption.

An audio processor card for special sound effects

The design of an audio processor card for generating special sound effects is presented. This is designed as an add-on card that plugs directly into the ISA bus of a PC. The card uses a Motorola DSP processor, DSP56001, for audio signal processing. External SRAM modules are used for program and data storage. A codec chip is employed to handle the digital interfacing between the DSP processor and the analog audio world.

A fast RNS Galois field multiplier

An approach to the design of a fast residue-number-system (RNS)-based multiplier over a Galois field GF(p), where p is a prime number, is presented. This design uses an isomorphic mapping from the additive index group, modulo (p-1,), of GF(p) onto a set of submodular additive groups. The submoduli are selected for minimizing the hardware and increasing the speed. This is accomplished by fully exploiting the properties of a Galois field. This multiplier is faster and uses less silicon area than previously published designs.<<ETX>>

Delay Efficient 32-bit Carry-Skip Adder

The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. The group generate and group propagate functions used in carry look ahead logic are used to speed up multiple stages of ripple carry adders. The optimum sizes for the skip blocks are decided by considering the critical path into account. The adder is implemented in 0.25 mum CMOS technology at 3.3 V. The simulation results showed a critical path delay of 3.4 ns, which translates to a speed improvement of 18% compared to the current fastest carry skip adder.

Delay Optimized Redundant Binary Adders

Redundant binary adders And wide applications in arithmetic circuits because of their constant time addition property. In this paper we present three redundant binary adders, the first one using a 4:2 compressor as the main logic block, the second one using a number of standard CMOS logic gates and the third one using transmission gates. The first two adders compare favorably against other competing adders in terms of simplicity of design and hardware used. Even though the third one uses more transistors in its implementation, it is faster than the fastest RBA cell reported in the literature.