Dan Kasha

A five stage chopper stabilized instrumentation amplifier using feedforward compensation

A programmable gain chopper stabilized instrumentation amplifier is presented. It uses a fifth order amplifier architecture with simulated open loop gain of 200 dB. It is the first reported silicon implementation of an amplifier using multipath feedforward compensation. The instrumentation amplifier achieves noise density of 7 nV/sqrt(Hz) and THD of -110 dB with 14 mW from a single 5 V supply. It is implemented in 0.6 /spl mu/m CMOS and has an active area of 4 mm/sup 2/.

A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing

A high resolution fourth-order ΔΣ ADC is presented. Power reduction techniques have been applied across many aspects of the design. A class-A amplifier was designed with bias currents optimized according to the expected activity in each clock phase. The modulator achieves a 122dB dynamic range over a 400Hz bandwidth, -123dB THD, and 16mW power consumption from a single 5V supply. It is implemented in a 0.6µm double polysilicon CMOS process, and has an active area of 2 mm2.

A 16 mW, 120 dB linear switched-capacitor delta-sigma modulator with dynamic biasing

A high resolution fourth-order ΔΣ ADC is presented. Power reduction techniques have been applied across many aspects of the design. A class-A amplifier was designed with bias currents optimized according to the expected activity in each clock phase. The modulator achieves a 122dB dynamic range over a 400Hz bandwidth, -123dB THD, and 16mW power consumption from a single 5V supply. It is implemented in a 0.6µm double polysilicon CMOS process, and has an active area of 2 mm2.

A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion

A one-bit digital-to-analog converter architecture is presented that reduces distortion through the use of feedback. The only critical circuit in this architecture is identical to the first integrator of a /spl Delta//spl Sigma/ analog-to-digital converter. All other circuits in the system are embedded in the feedback loop, which reduces the effects of their nonidealities. Special attention was given to the distortion arising from the discrete-time to continuous-time interface. The feedback loop is a conditionally stable system using multipath feedforward compensation. A total harmonic distortion of -110 dB is achieved. The signal-to-noise ratio is 114 dB in 400 Hz, and out-of-band noise is below -50 dB using only one external component. The power consumption is 18 mW from a 5-V supply. Die area is 3.6 mm/sup 2/ in 0.6-/spl mu/m DPTM-CMOS technology.

A 110 dB THD, 18 mW DAC using output sampling and feedback to reduce distortion

A digital-to-analog converter (DAC) with -110 dB total harmonic distortion (THD) is required to generate signals for linearity tests of data acquisition channels and sensors. Low power and a minimal number of external components are important to the application. A 256 kHz noise shaped bit stream is provided with a maximum signal frequency of 100 Hz. The out-of-band quantization noise has to be attenuated to less than -50 dB. A topology that minimized the number of critical circuit blocks in the DAC is preferable to minimize the design tasks and risks.