Dan Ritter

Steady‐state photocarrier grating technique for diffusion length measurement in photoconductive insulators

A new simple technique for the determination of the diffusion length in photoconductive insulators is presented. A steady‐state photocarrier grating is created by two interfering laser beams, and the magnitude of the secondary photocurrent perpendicular to the grating fringes is measured. The measurement is then repeated when the two beams are incoherent. From a determination of the two photocurrents as a function of grating period the diffusion length of the photocarriers can be obtained. The method can yield accurate results to 5% of the laser wavelength.

Steady‐state photocarrier grating technique for diffusion‐length measurement in semiconductors: Theory and experimental results for amorphous silicon and semi‐insulating GaAs

The theory underlying the steady‐state photocarrier grating technique is presented, including the effect of surface recombination. Experimental results for amorphous hydrogenated silicon and semi‐insulating GaAs prove that diffusion lengths ranging from 200 A to 10 μm can be measured with an accuracy of better than 5%.

Formation of InAs self-assembled quantum rings on InP

Shape transformations of partially capped self-assembled InAs quantum dots grown on InP are studied. Atomic force microscopy images show large anisotropic redistribution of the island material after coverage by a 1-nm-thick InP layer. The anisotropic material redistribution occurs within a few minutes and leads to a change from lens-like to elongated ring-like islands. The shape transformation is not accompanied by dot material compositional change. The formation of InAs/InP quantum rings disagrees with a previous model of InAs/GaAs ring formation that assumes that the driving force for the dot to ring transformation is the difference in surface diffusion velocity of indium and gallium atoms.

Extraction of the InP/GaInAs heterojunction bipolar transistor small-signal equivalent circuit

An extraction technique for determining the small-signal equivalent circuit model of an InP/GaInAs heterojunction bipolar transistor is presented. The equivalent circuit includes the extrinsic base collector capacitance and extrinsic base resistance. It is clearly indicated which elements are uniquely determined, and which elements are estimated. >

Electrical characteristics of metal-dielectric-metal and metal-dielectric-semiconductor structures based on electron beam evaporated Y2O3, Ta2O5 and Al2O3 thin film

This work examines the electrical properties of metal-dielectric-semiconductor (Au/Ti–D–pSi) and metal-dielectric-metal (Au/Ti–D–Pt/Ti–pSi) capacitors which incorporate as dielectrics Y2O3, Al2O3 and Ta2O5 films evaporated by an electron beam at room temperature. The emphasis of the results is twofold: the first is the high quality of the investigated films as evidenced by the small measured values of loss factor, flatband voltages, and surface states density as well as the low dispersion of the relative dielectric constants. The second is an analytical procedure for discrimination of current flow mechanisms, under different regimes of applied voltage. A detailed study of the power exponent parameter α=d(Log I)/d(Log V) was found to be superior to conventional graphical representation of I–V data. The dominant mechanisms of charge transport through the metal-dielectric-metal structures was found to be the Schottky emission for Y2O3 and Al2O3 at low electrical fields. For structures with Y2O3 and Ta2O5 fil...

Compact metalorganic molecular‐beam epitaxy growth system

This article describes a compact growth system specifically designed for metalorganic molecular‐beam epitaxy (MOMBE) of InP‐based materials. The system is designed to take full advantage of the MOMBE method, in particular the premixing of the group III and V precursors, respectively, and the elimination of large solid effusion cells. The system uses a fixed sample heating stage which is designed for indium wafer mounting, up to a 2 in. diameter, on molybdenum blocks. Temperature control during growth is done with a thermocouple inserted directly into the sample block with a small charge of indium to provide intimate thermal contact. Sample loading is done vertically from above in order to load the sample in the growth position. The system is controlled by a personal computer, which also replaces all of the analog temperature and pressure controllers. Initial results on 2‐in. diameter wafers indicate excellent uniformity of the composition, Δa/a=±2×10−4 for InGaAs, and photoluminescence, ±4.5 nm for InGaAs...

A CMOS Bidirectional 32-Element Phased-Array Transceiver at 60 GHz With LTCC Antenna

Fully integrated 32-element symmetrical TX/RX 60-GHz RF integrated circuit (RFIC) with built-in self-test is presented. The RF bidirectional power-combining architecture with shared blocks and less than 1-dB millimeter-wave transmit/receive (T/R) switch loss achieves record size and power consumption. The RFIC features an 8-dB noise figure and - 28-dBm IP1 dB in RX mode, 10-dB power gain, and Psat of +3.5 dBm per chain in TX mode. Further included are a 2-bit phase shifter, an IF converter to/from 12 GHz, and an integrated frac-N synthesizer with push-push voltage-controlled oscillator having a-93 dBc@1-MHz phase noise at 48-GHz local oscillator port. A novel high dynamic range phase and power detector is presented with 2° and ±1-dB accuracy over PVT in phase and power. A detailed analysis of both phase quantization and power distribution is presented. Array impairments such as mismatch and coupling were compared for different topologies. The RFIC is packaged on alumina for testing and on low-temperature co-fired ceramic (LTCC) for antenna integration. The 6 × 6 patch antenna on LTCC including four dummies achieves a gain of 19 dBi with scanning of ± 30°. The total root mean square amplitude and phase error of the array is 0.8 dB and 6° , respectively, resulting in a maximum array beam degradation of 1.4 dB for 2-bit quantization. The RFIC area is 29 mm2 and it consumes 1.2 W/0.85 W at TX/RX, with a 29-dBm effective isotropic radiated power at -19-dB error vector magnitude.

On the extraction of linear and nonlinear physical parameters in nonideal diodes

We describe a parameter extraction technique for the simultaneous determination of physical parameters in nonideal Schottky barrier, p-n and p-i-n diodes. These include the ideality factor, saturation current, barrier height, and linear or nonlinear series, and parallel leakage resistances. The suggested technique which deals with the extraction of bias independent parameters makes use of the forward biased current–voltage (I–V) characteristics and the voltage-dependent differential slope curve α(V)=[d(ln I)]/[d(ln V)]. The method allows (a) establishment of the current flow mechanisms at low and high bias levels, (b) extensive of the permissible ranges of determined parameters beyond what is possible in other published methods, and (c) to automation and computerization of the measurement processes. The method is verified experimentally using metal–semiconductor structures based on Si, InGaP, and HgCdTe as well as an InGaAs/InGaAsP multiple quantum well laser diode exemplifying a p-n junction.

A Bidirectional TX/RX Four-Element Phased Array at 60 GHz With RF-IF Conversion Block in 90-nm CMOS Process

A 60-GHz four-element bidirectional phased-array transmitter/receiver (TX/RX) chip with a two bit phase shifter (PS) and IF converter to/from 12 GHz, using a 90-nm CMOS process, is described. The array features 7-dB gain, measured noise figure of 9 dB, IPldB of -19 dBm for RX, and output Psat of +3.5 dBm for TX, drawing 60 mA from a 1.3-V supply. The rms amplitude and phase error of the PS is 0.7 dB and 2° max, respectively, from 57 to 66 GHz. This new architecture, together with the compact layout, decreases chip size by a factor of 2, compared to a separate TX and RX design. The use of passive PSs and combiners reduces the current consumption and minimizes temperature variation. An additional rms error of 0.3° and 0.07 dB was measured from 0°C to 80°C. Total die area is 1.6 × 1 mm2 and 1.6 × 0.65 mm2 with and without an IF converter block, respectively. First pass success was achieved by the closed ground environment design methodology of the passive structures and by proper layout. To our knowledge, this is the first report on a bidirectional 60-GHz array with the lowest reported chip power consumption and size.

An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio

This paper presents a 60 GHz LNA designed in a 90 nm CMOS process with 6 metals Cu thick metal, and Ft/Fmax of 100 GHz/150 GHz demonstrating best known noise figure, gain, power consumption and size compared to earlier 60-GHz LNAs reported. It features 15 dB of gain, a measured noise figure (NF) of 4.4 dB, while drawing 3 mA from a 1.3-V supply. The use of spiral inductors enables a reduction in transistor size, total power consumption, and die size. The LNA die area with/without pads is 0.32times0.44 mm2/0.14times0.27 mm2 respectively. First pass success was achieved by proper methodology of closed ground environment for passive structures and proper layout. The paper compares different transistor core sizes and different circuit topologies showing that a common source (CS) topology with a 10times1 um transistor width gives the best performance over all other options.