Emanuel Cohen

A CMOS Bidirectional 32-Element Phased-Array Transceiver at 60 GHz With LTCC Antenna

Fully integrated 32-element symmetrical TX/RX 60-GHz RF integrated circuit (RFIC) with built-in self-test is presented. The RF bidirectional power-combining architecture with shared blocks and less than 1-dB millimeter-wave transmit/receive (T/R) switch loss achieves record size and power consumption. The RFIC features an 8-dB noise figure and - 28-dBm IP1 dB in RX mode, 10-dB power gain, and Psat of +3.5 dBm per chain in TX mode. Further included are a 2-bit phase shifter, an IF converter to/from 12 GHz, and an integrated frac-N synthesizer with push-push voltage-controlled oscillator having a-93 dBc@1-MHz phase noise at 48-GHz local oscillator port. A novel high dynamic range phase and power detector is presented with 2° and ±1-dB accuracy over PVT in phase and power. A detailed analysis of both phase quantization and power distribution is presented. Array impairments such as mismatch and coupling were compared for different topologies. The RFIC is packaged on alumina for testing and on low-temperature co-fired ceramic (LTCC) for antenna integration. The 6 × 6 patch antenna on LTCC including four dummies achieves a gain of 19 dBi with scanning of ± 30°. The total root mean square amplitude and phase error of the array is 0.8 dB and 6° , respectively, resulting in a maximum array beam degradation of 1.4 dB for 2-bit quantization. The RFIC area is 29 mm2 and it consumes 1.2 W/0.85 W at TX/RX, with a 29-dBm effective isotropic radiated power at -19-dB error vector magnitude.

A Bidirectional TX/RX Four-Element Phased Array at 60 GHz With RF-IF Conversion Block in 90-nm CMOS Process

A 60-GHz four-element bidirectional phased-array transmitter/receiver (TX/RX) chip with a two bit phase shifter (PS) and IF converter to/from 12 GHz, using a 90-nm CMOS process, is described. The array features 7-dB gain, measured noise figure of 9 dB, IPldB of -19 dBm for RX, and output Psat of +3.5 dBm for TX, drawing 60 mA from a 1.3-V supply. The rms amplitude and phase error of the PS is 0.7 dB and 2° max, respectively, from 57 to 66 GHz. This new architecture, together with the compact layout, decreases chip size by a factor of 2, compared to a separate TX and RX design. The use of passive PSs and combiners reduces the current consumption and minimizes temperature variation. An additional rms error of 0.3° and 0.07 dB was measured from 0°C to 80°C. Total die area is 1.6 × 1 mm2 and 1.6 × 0.65 mm2 with and without an IF converter block, respectively. First pass success was achieved by the closed ground environment design methodology of the passive structures and by proper layout. To our knowledge, this is the first report on a bidirectional 60-GHz array with the lowest reported chip power consumption and size.

An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio

This paper presents a 60 GHz LNA designed in a 90 nm CMOS process with 6 metals Cu thick metal, and Ft/Fmax of 100 GHz/150 GHz demonstrating best known noise figure, gain, power consumption and size compared to earlier 60-GHz LNAs reported. It features 15 dB of gain, a measured noise figure (NF) of 4.4 dB, while drawing 3 mA from a 1.3-V supply. The use of spiral inductors enables a reduction in transistor size, total power consumption, and die size. The LNA die area with/without pads is 0.32times0.44 mm2/0.14times0.27 mm2 respectively. First pass success was achieved by proper methodology of closed ground environment for passive structures and proper layout. The paper compares different transistor core sizes and different circuit topologies showing that a common source (CS) topology with a 10times1 um transistor width gives the best performance over all other options.

A thirty two element phased-array transceiver at 60GHz with RF-IF conversion block in 90nm flip chip CMOS process

A 60 GHz 32 element bidirectional phase-darray TX/RX chip with a 2 bit phase shifter and IF converter to/from 12GHz, using 90nm CMOS process, is described. The array features 12.5 dB gain, noise figure (NF) of 11 dB, IP1dB of −17dbm for RX, and total output Psat of +8dBm for TX, drawing 390 mA from a 1.3-V supply. The RMS amplitude and phase error of the phase shifter is 0.8dB and 5° max respectively from 57 to 66 GHz. The paper emphasizes the flip-chip assembly technology selected and its impact on performance, and the phase and amplitude errors resulted by physical impairments such as the finite isolation between different chains. Special test structures were designed to measure bump isolation and insertion loss (IL). The designed architecture together with the compact layout results in a die area of 14.5mm2 for the full array. To our knowledge, this is the first report on a large bidirectional 60 GHz array, with the lowest reported chip power consumption and size.

A bidirectional TX/RX four element phased-array at 60GHz with RF-IF conversion block in 90nm CMOS process

A 60 GHz 4 element bidirectional phased-array TX/RX chip with a 2 bit phase shifter and IF converter to/from 12GHz, using 90nm CMOS process, is described. The array features 7 dB gain, measured noise figure (NF) of 9 dB, IP1dB of −19dbm for RX, and output Psat of +3.5dBm for TX , drawing 60 mA from a 1.3-V supply. The RMS amplitude and phase error of the phase shifter is 0.7dB and 2° max respectively from 57 to 66 GHz. This new architecture together with the compact layout decreases chip size to about half compared to a separate TX and RX design. The use of passive phase shifters and combiners reduce the current consumption. Total die area is 1.6×1 mm2 with half of the area being the IF converter block. First pass success was achieved by the closed ground environment design methodology of the passive structures and by proper layout. To our knowledge, this the first report on a bidirectional 60 GHz array, with the lowest reported chip power consumption and size.

A CMOS bidirectional 32-element phased-array transceiver at 60GHz with LTCC antenna

Fully integrated 32-element symmetrical TX/RX 60-GHz RF integrated circuit (RFIC) with built-in self-test is presented. The RF bidirectional power-combining architecture with shared blocks and less than 1-dB millimeter-wave transmit/receive (T/R) switch loss achieves record size and power consumption. The RFIC features an 8-dB noise figure and - 28-dBm IP1 dB in RX mode, 10-dB power gain, and Psat of +3.5 dBm per chain in TX mode. Further included are a 2-bit phase shifter, an IF converter to/from 12 GHz, and an integrated frac-N synthesizer with push-push voltage-controlled oscillator having a-93 dBc@1-MHz phase noise at 48-GHz local oscillator port. A novel high dynamic range phase and power detector is presented with 2° and ±1-dB accuracy over PVT in phase and power. A detailed analysis of both phase quantization and power distribution is presented. Array impairments such as mismatch and coupling were compared for different topologies. The RFIC is packaged on alumina for testing and on low-temperature co-fired ceramic (LTCC) for antenna integration. The 6 × 6 patch antenna on LTCC including four dummies achieves a gain of 19 dBi with scanning of ± 30°. The total root mean square amplitude and phase error of the array is 0.8 dB and 6° , respectively, resulting in a maximum array beam degradation of 1.4 dB for 2-bit quantization. The RFIC area is 29 mm2 and it consumes 1.2 W/0.85 W at TX/RX, with a 29-dBm effective isotropic radiated power at -19-dB error vector magnitude.

A wideband gain-boosting 8mW LNA with 23dB gain and 4dB NF in 65nm CMOS process for 60 GHz applications

A three stage single-ended LNA using transformer (TF) matching and gain-boosting by capacitive feedback for wideband operation in the 57-66GHz band is presented. The LNA, fabricated in a 65nm standard CMOS process, achieves a 23dB-gain 4dB NF at 6mA and 1.25V supply, with 2dBm Psat and 0.05mm2 in size, demonstrating best reported noise figure, gain, power consumption and chip area compared to published 60 GHz LNAs. Different neutralization topologies were analyzed and compared based on analytical TF models that were created. Optimal gain-boosting is achieved by capacitive feedback after a 180-deg TF together with special decoupling capacitors of MOM and MOS stacked types.

60GHz 45nm PA for linear OFDM signal with predistortion correction achieving 6.1% PAE and −28dB EVM

A 45nm CMOS 60 GHz PA optimized for linear modulation with 6dbm saturated power and 13dB gain is presented when biased at 70uA/um. A maximum power added efficiency (PAE) of 19.4% 8dBm Psat and 18dB gain is achieved for 200uA/um bias point. The PA was tested using a predistortion algorithm and OFDM packets, and achieved PAE of 6.1% with −28dB EVM and 9% with −20dB EVM at output powers of −2dBm and +1dBm respectively. To our knowledge this is the first publication of a 45nm PA design analyzing the tradeoff between EVM and PAE at the 60 GHz frequency range and using predistortion algorithms to boost efficiency and power.

75 GHz InP HBT distributed amplifier with record figures of merit and low power dissipation

We present an InP HBT distributed amplifier with a bandwidth of 75 GHz, gain of 14 dB, and power consumption of 78 mW. The HBTs had a 600 nm thick collector, and hence relatively low fT and fMAX of 84 GHz and 150 GHz respectively. The thick collector is a tradeoff required in optoelectronic integrated receivers, in which the PIN diode layers are the same as the base collector layers. To obtain high PEN diode responsivity, the collector layer needs to be thicker than in optimized HBTs. The amplifier topology comprises an emitter follower at the input and a cascode stage, with a resistor and inductance at the emitter follower output, and a peaking line between the HBTs in the cascode stage. The amplifier exhibits matching at the input better than -10 dB up to 85 GHz. The chip contains 16 HBTs and it size is 1.7mm times 0.9 mm

A 102–129-GHz 39-dB Gain 8.4-dB Noise Figure I/Q Receiver Frontend in 28-nm CMOS

An F-band in-phase/quadrature-phase (I/Q) receiver front-end in 28-nm CMOS for chip-to-chip communication is presented. The receiver consists of a capacitively neutralized differential low-noise amplifier (LNA) chain, a passive ring mixer, zero-IF drivers, and a novel tunable transformer-based quadrature splitter. This paper discusses the effect of capacitive neutralization on common-mode stability, matching losses, and the noise performance of a differential pair. A technique for gain and noise-figure optimization by core sizing and partial neutralization is presented. The receiver exhibits a gain of 39 dB, a 3-dB RF bandwidth of 27 GHz, a noise figure between 8.4 and 10.4 dB, and a P1 dB of 3.2 dBm. The receiver front-end consumes 18 mW from a 1.0-V supply and the baseband I and Q buffers consume a total of 33 mW from a 1.5-V supply. A breakout of the LNA shows a measured gain of 21 dB, a noise figure of 8.0-9.4 dB, with a gain power efficiency of 1.2 dB/mW around 125 GHz.