Dan W. Patterson

Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant Logic

A fully automated logic design methodology for radiation hardened by design high-speed logic using fine-grained triple modular redundancy (TMR) is presented. The methodology and circuits leverage commercial logic design automation tools. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. The base TMR self-correcting master-slave flip-flop is described, including testability features that disable the self-correction. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g., clock gating and supply voltage scaling.

High speed redundant self-correcting circuits for radiation hardened by design logic

Self-correcting fine-grained triple redundant circuits using majority gate feedback for single event upset and transient radiation hardening are described and compared to other hardening approaches. The approach votes the triple modular redundant (TMR) state in the state element feedback path, which allows high performance commensurate with commercial integrated circuits. Clock gating is supported. The TMR self-correcting approach is used in a built-in self-test engine to evaluate a 16 k-byte cache design. The circuits have been fabricated on a 90 nm low standby power bulk CMOS process. Data paths have been tested at clock frequencies up to 500 MHz. TID tests using Co-60 indicate negligible standby current increase at over 2 Mrad(Si) and ion tests show SEE hardness beyond 100 MeV-cm2/mg LET.

A Dual Mode Redundant Approach for Microprocessor Soft Error Hardness

A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

Single event transient mitigation in cache memory using transient error checking circuits

Protecting a high performance radiation hardened by design (RHBD) cache from single-event transient (SET) induced peripheral circuit errors is presented. Cache memory holds processor architectural state and peripheral errors can cause incorrect operations that affect entire data words, including parity. Thus, a periphery circuit, e.g., word-line, error can be induced that results in silent data corruption, for instance by writing two locations at once. The design presented here includes checking circuits to detect potential SET induced errors, allowing mitigation by invalidation of the write-through cache blocks. A 16 kB cache and test engine, fabricated on an IBM 90 nm bulk CMOS process, irradiated with heavy ions, is used to provide experimental validation of the design.

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart - only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm2/mg LETEFF. We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.