Nathan D. Hindman

The Impact of Total Ionizing Dose on Unhardened SRAM Cell Margins

Static random access memory (SRAM) cells have diminishing read and write margins due to fabrication variations. These variations are a direct result of the small device sizes necessary to maintain scaling commensurate with Moores law. Total ionizing dose (TID) primarily affects NMOS device characteristics, which are the most important to maintaining SRAM cell read stability. A test structure allowing direct measurement of SRAM cell electrical characteristics in an SRAM memory bank is presented. Experimentally measured results from this structure, fabricated on a 90 nm process, show impact of Co-60 irradiation on SRAM cell margins. This test structure is fabricated on the same die as a 1.2 Mbit SRAM, allowing comparison of the individual cell characteristics with the overall leakage impact on the large SRAM. The results indicate that by simply providing sufficient margins during SRAM cell design, functionality at high TID can be achieved without the use of radiation hardening by design (RHBD) techniques. The implications for future unhardened SRAMs operating in TID environments and on design to maintain margins are discussed.

Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant Logic

A fully automated logic design methodology for radiation hardened by design high-speed logic using fine-grained triple modular redundancy (TMR) is presented. The methodology and circuits leverage commercial logic design automation tools. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. The base TMR self-correcting master-slave flip-flop is described, including testability features that disable the self-correction. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g., clock gating and supply voltage scaling.

High speed redundant self-correcting circuits for radiation hardened by design logic

Self-correcting fine-grained triple redundant circuits using majority gate feedback for single event upset and transient radiation hardening are described and compared to other hardening approaches. The approach votes the triple modular redundant (TMR) state in the state element feedback path, which allows high performance commensurate with commercial integrated circuits. Clock gating is supported. The TMR self-correcting approach is used in a built-in self-test engine to evaluate a 16 k-byte cache design. The circuits have been fabricated on a 90 nm low standby power bulk CMOS process. Data paths have been tested at clock frequencies up to 500 MHz. TID tests using Co-60 indicate negligible standby current increase at over 2 Mrad(Si) and ion tests show SEE hardness beyond 100 MeV-cm2/mg LET.

A Dual Mode Redundant Approach for Microprocessor Soft Error Hardness

A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

Temporal sequential logic hardening by design with a low power delay element

A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient (SET) tolerance is demonstrated by simulations using it in a radiation hardened by design (RHBD) master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element incorporates redundancy to mask long transients, which would otherwise limit the circuit hardness. Two FF layouts using the proposed delay element are used in synthesis and auto-place and route experiments to confirm overall power, performance, and density. The first (interleaved) version uses a multi-bit cell interleaving the constituent circuits of four FFs. The second (inline) version interleaves the master and slave circuits to achieve high density while maintaining adequate critical node separation. The latter is shown to be more power efficient and the former is more robust to multiple node collection.

Validation of and delay variation in total ionizing dose hardened standard cell libraries

A ring oscillator based test structure with special power multiplexing to allow accurate active and standby (leakage) power measurements with minimal test chip pin count is presented. This structure is used to validate radiation hardened by design (RHBD) standard cell library gates for TID hardness and delay. Additionally, the performance of standard commercial two-edge gates and their annular counterparts are also compared experimentally. The gate delay and energy per transition is shown to be significantly increased for some RHBD gates over their two-edge counterparts. Large ring oscillator delay variations are also shown, even with all test die from the same wafer.

Design and Experimental Validation of Radiation Hardened by Design SRAM Cells

The design and electrical characterization of a total ionizing dose hardened by a design static random access memory (SRAM) cell using annular layout and guard rings are presented. Since foundry SRAM cells can be validated during process development and manufacturing ramp but radiation hardening by design cells cannot, we use a specialized test structure to validate the cell design here. Stability, manufacturability, and hardness are experimentally investigated using a 4 kbit SRAM structure, fabricated on one version of the foundry 90 nm process. The structure, combined with a novel test and simulation based extraction procedure, allows direct measurement of the as-fabricated cell electrical characteristics. Variation of the SRAM switching points due to irradiation as well as the individual transistor threshold voltage variability is measured in the SRAM array test structure. Irradiation tests show negligible impact on switching voltage and increase in the standby current less than 1.5% after 2 Mrad(Si). The effects on the cell margins are also analyzed. The specific SRAM cell layout, which uses a very low aspect ratio, is intended to minimize multibit upset of horizontally adjacent cells. This impact is also discussed with measured heavy ion results.

Experimentally Measured Input Referred Voltage Offsets and Kickback Noise in RHBD Analog Comparator Arrays

Analog comparator arrays fabricated on a bulk CMOS 130-nm are measured to quantify input-referred offsets due to transistor variation and kickback noise. Comparators using RHBD edgeless and conventional two-edge transistors are compared to determine the impact on the circuit behavior. Both random variation and kickback noise are slightly larger than for an equivalent design using two-edge transistors. The input-referred offsets are shown to be completely systematic.

In-situ characterization and extraction of SRAM variability

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new single-ended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90 nm test chip with 32 K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasi-static control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90 nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is <; 4% at all corners.