Daniel Audet

Pipelining communications in large VLSI/ULSI systems

A simple and very effective solution to the delay incurred while propagating data through long interconnection wires is presented. Such delays can be found in large VLSI/ULSI or wafer scale systems. The basic idea of the technique relies on the fragmentation of the wires and in reconnecting them with a special device called repeater in order to form a bidirectional pipeline. A method for determining the optimum configuration of the pipeline is presented. It is shown that, even in presence of an appreciable skew in synchronous systems, the technique improves the transmission speed by 150% for 32-byte messages, when a 10 cm 8-bit bus implemented in a 1.2 /spl mu/m CMOS technology is used. The improvement increases for longer messages and for larger skews. It is also shown that the actual transmission time is close (to within a factor of 2) to the theoretical limit that could be achieved with a zero-length wire. A method based on repeaters operating at a multiple of the basic system clock frequency is also proposed. It is shown that this technique may speedup data transfer by an order of magnitude. The extension of the technique to asynchronous self-timed repeaters is also discussed. Finally, a VLSI implementation of the synchronous reconnection device is described. >

Reducing fault sensitivity of microprocessor-based systems by modifying workload structure

The use of off-the-shelf components in microprocessor-based systems can limit the applicability of a number of hardware fault-tolerance methods. Software techniques offer attractive solutions to improve the reliability of systems operating in a hostile environment. The fault sensitivity of a system running a critical application obviously depends on the application execution time and the amount of memory it uses. This study shows that the program structure also has a significant influence on fault sensitivity. Program characteristics, such as the size and duration of iterative and sequential sections, are required to determine the sensitivity profile. It is shown that, provided data dependency is not affected one can rearrange the program structure to significantly reduce the average sensitivity of a program. Straightforward analysis of the sensitivity profile allows one to estimate the reduction. A simple example of code rearrangement is described and it is shown that a 50% reduction could be achieved with respect to the initial structure. The magnitude of the reduction varies from one application to another.

An architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems

Based on a special pipelining technique, a new methodology for increasing the clock frequency and communication speed in monolithic WSI systems is proposed. SPICE simulations show that the clock frequency on a synchronous wafer-scale system, implemented using a 1.2 /spl mu/m CMOS technology, can be operated well above 140 MHz, which is approximately five times the maximum frequency of current systems. It is also shown that frequencies higher than 1 GHz can be achieved if the technique is pushed to its limits. The methodology can be applied to interconnection networks as well, thereby improving their speed by approximately the same factor. In order to assess the various design tradeoffs imposed by the technique, a prototype communication interface has been designed using 1.2 /spl mu/m CMOS standard cells. This interface is intended to be used in a special distributed-queue, dual-bus (DQDB) communication network. >

Harvest model of an integrated hierarchical-bus architecture

This paper presents a new approach to model the yield of a fault-tolerant hierarchical-bus structure, based on the expected value of the number of functional processors. With this method, easily computable mathematical expressions were obtained. Also, a defect tolerant communication network structure is proposed and analyzed in terms of additional hardware cost versus spares allocation. Assuming the network was successfully repaired, global reconfiguration of defective processing modules is then supported. Otherwise some graceful degradation would result. The results obtained, in terms of optimal distribution of spares in the communication network, show that complete duplication is not cost effective. However, redundancy can be added to the uppermost levels of the hierarchical tree in a very effective manner. Two harvest formulas were obtained; the first is an easily computed lower bound, and the second is exact according to the assumed defect density.<<ETX>>

High-speed interconnections using true single-phase clocking

Long interconnections in wafer scale systems can severely limit their operating frequency and the speed of data transfers between distant components. One way to significantly improve these parameters consists in converting long wires into synchronous pipelines. For this purpose, a high-speed pipeline stage has been designed using a state-of-the-art circuit design methodology: single-phase clocking. This methodology usually allows one to design faster circuitries with lower transistor counts. Based on SPICE simulations, it is shown that the designed pipeline stage can transfer data at rates above 800 Mbits/s per wire, when a 1.2 /spl mu/m CMOS technology is used. In order to estimate the maximum data rate when such pipeline stages are used in a practical situation, SPICE simulations were also carried out by interconnecting them using 1 cm metallic wire segments. It is shown that, in this case, data transfer rates larger than 300 Mbits/s can be reached.

Performance models for optimizing a hierarchical-bus multiprocessor architecture

In order to build high-performance multiprocessor systems that take advantage of current VLSI technologies, a new architecture, called Hierarchical-Bus Multiprocessor Architecture, has been proposed. This paper develops analytical models for the performance analysis of its communication network. The performance index used for comparisons is the mean response time of the communication network. To keep the analysis tractable, some simplifying assumptions were made. Due to the size of the complete queueing network model, an approximate model was developed. Validation of the analytical model against a simulation study reveals that this model predicts performance of the communication network architecture with adequate accuracy.<<ETX>>

Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources☆

Abstract This paper presents a new approach for improving the efficiency of large VLSI parallel systems called the Dynamic Concatenation Approach (DCA). The basic idea of DCA is to concatenate bit-serial processing elements to construct bit-parallel processors of variable width. The concatenation permits an increase in the storage capacity of each processor which can be used to keep a number of local variables within the processor registers. A model for evaluating the performance speed-ups that could be achieved using DCA is developed. Arbitrary architectural characteristics as well as program characteristics are both taken into account in this model. Speed-up estimates are obtained by considering the effect of DCA when the variables of three programs are allocated to the registers of the processing elements. It is shown that DCA significantly improves performance in systems where I/O bottlenecks exist.