Yvon Savaria

Reconfigurable pipelined 2-D convolvers for fast digital signal processing

In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developers toolset. In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSPs, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolvers design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated. However, the proposed concept is not limited to a particular processor.

A comparison of automatic word length optimization procedures

This paper presents a comparison of word length determination procedures. It is realized using an automated testbed that exploits a C/C++ fixed-point simulation utility to model the impact of finite word length on overall accuracy. Word length determination procedures find a combination of optimum bit resolutions by computing dissimilarities between fixed-point and floating-point simulation results. The comparison helps to select a procedure that minimizes these dissimilarities and finds an optimal combination of word lengths that meet user specified objectives, in a minimum number of iterations and hardware cost. This comparison was applied on various DSP algorithms.

Software detection mechanisms providing full coverage against single bit-flip faults

Increasing design complexity for current and future generations of microelectronic technologies leads to an increased sensitivity to transient bit-flip errors. These errors can cause unpredictable behaviors and corrupt data integrity and system availability. This work proposes new solutions to detect all classes of faults, including those that escape conventional software detection mechanisms, allowing full protection against transient bit-flip errors. The proposed solutions, particularly well suited for low-cost safety-critical microprocessor-based applications, have been validated through exhaustive fault injection experiments performed on a set of real and synthetic benchmark programs. The fault model taken into consideration was single bit-flip errors corrupting memory cells accessible to the user by means of the processor instruction set. The obtained results demonstrate the effectiveness of the proposed solutions.

A High-Efficiency Low-Voltage CMOS Rectifier for Harvesting Energy in Implantable Devices

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

Automatic test point insertion for pseudo-random testing

A combination of techniques for efficiently inserting test points is proposed. These techniques refer to three complementary abstraction levels: algorithms, circuits, and layout. The authors deal with pseudo-random testing and present a method of condensing test points based on the notion of fault sector. Based on a set of proposed heuristics, a tool for automatically inserting test points was developed. Experimental results obtained with the tool are presented to indicate that excellent pseudo-random testability can be achieved with few test points. This technique leads to the lowest reported number of test points while significantly reducing the number of random patterns which are required to achieve very close to 100% fault coverage.<<ETX>>

Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits

As the semiconductor industry continues to scale down the feature sizes in VLSI digital circuits, soft errors will eventually limit the reliability of these circuits. An important source of these errors will be the products of radioactive decay. It is proposed to combat these transient errors by a new technique called soft-error filtering (SEF). This is based on filtering the input to every latch in the VLSI circuit, thereby preventing these transients, generated by alpha particle hits in the combinational section, from being latched in the corresponding registers. Several approaches to the problem of designing filtering latches are compared. This comparison demonstrates the superiority of a double-filter realization. The design for a CMOS implementation of the double-filter latch is presented. Not only is the design simple and efficient, but it can be expected to be tolerant to process variations. A comparison of SEF with conventional techniques for dealing with soft errors shows the former to be generally much more attractive, from the point of view of both area and time overhead.

System Design of an Integrated Measurement Electronic Subsystem for Bacteria Detection Using an Electrode Array and MC-1 Magnetotactic Bacteria

This paper presents a novel technique for bacteria detection. The proposed system uses MC-1 magnetotactic bacteria and measures impedance to detect the presence of pathogenic bacteria. An electrode array is connected to respective cells that are fully integrated for impedance detection. The simulated performance shows that the circuit that was designed is robust. It can detect impedances ranging from about 3 KOmega to at least 100 MOmega. The only limits that we have for detecting large impedances are the operation frequencies and leakage currents. The circuit is thus very robust and can adapt to a wide range of uncertainty.

An automatic word length determination method

A method to determine the word length required by implementations of Digital Signal Processing (DSP) algorithms is presented. The method uses a C/C++ fixed-point simulation tool to model the impact of finite word length on overall accuracy. It finds a combination of quasi-optimum bit resolutions in arbitrary data flow graphs by computing dissimilarities between fixed-point and floating-point simulation results. The selected algorithm minimizes these dissimilarities and finds a combination of word lengths that meets objectives specified by the user. This method is applicable to a wide range of DSP algorithms. It was tested on 2 benchmarks, the fifth order elliptic filter and the Inverse Discrete Cosine Transform (IDCT), and arrived to known optimum solutions.

Optimal methods of driving interconnections in VLSI circuits

Techniques for driving long interconnections in VLSI circuits are considered. Methods based on regularly inserted repeaters are reviewed, and it is shown that one of these is optimal. The main conclusions are that with the most accurate model of an interconnection (a pi -model) used, the optimal repeater is an appropriately sized inverter and that, when the interconnection is resistive, a double-stage repeater performs better than an exponential horn of inverters.<<ETX>>

A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs

Video signal processing requires complex algorithms performing many basic operations on a video stream. To perform these calculations in real-time in a FPGA, we must use innovative structures to meet speed requirements while managing complexity. As part of a project aiming at the development of a video noise reducer, we developed an optimized processing stream that required some floating-point calculations. This paper presents the rationale for developing a floating-point unit, justifies the data representation used, its implementation in a Xilinx VirtexE FPGA and reports the performance we obtained. A divider using this representation is also presented, with its implementation and performances in the same FPGA.