Daniel Henry

Review Of CD Measurement And Scatterometry

Scanning Electronic Microscopes (SEM) are widely used either for cross‐section measurement (process development) or for top‐down CD measurement (production). ITRS roadmap for CD and overlay metrology points out some difficult challenges for next technology nodes. Up to now, we remained confident respectively in SEM capability and in bright field microscopy for next node requirements. Today, the limit of 0.1 micron is crossed and new requirements are stated for new 300 mm fabs. Demands arise for tighter precision, complex profile metrology and fully non‐destructive control for in‐line and integrated tools. Scatterometry is an alternative solution for CD and overlay metrology, recently introduced in fabs. We propose to review the capability of scatterometry actually demonstrated in fab and potential extensions targeting 65nm technology node. The use of optical CD tools in a production environment has also been assessed for various applications. Finally, an overview of capability extension will be given.

65 nm device manufacture using shaped E-Beam lithography

In this paper, SRAM cell device manufacture using shaped electron beam lithography was developed. TEM view of SRAM cell was showed.

Application of spectroscopic scatterometry method in hole matrices analysis

This paper focuses on the capability of the spectroscopic scatterometry method to determine holes features parameters from experimental 3D-target. Scatterometry uses optical tools for spectra recording as ellipsometer form KLA TENCOR and a MMFE (Modal Method of Fourier Expansion) software tool including an advanced electromagnetic simulator and an optimization loop for data extraction. This study reports on 3D-MMFE regression of different dense holes square and rectangular matrix structures on the simplest structure-resist on silicon-to extract diameter, height of the holes. The holes diameter is from 90nm to 500nm, and the duty ratio is from 1:1 to 2:2 (CD/Space). To be close to real production stack the same matrices have been studied on more complex stack (close to via level with different dielectric material: FSG, dense SiOC). Finally this study is focused on an analysis on simulation and experiment of the relative sensitivity position of a hole inside the basic element of diffraction. That shows the possibility of scatterometry measurement in detecting via shift.

Spectroscopic ellipsometry for lithography front-end level CD control: a complete analysis for production integration

Using scatterometry based on Spectroscopic Ellipsometry, a complete study of Gate lithography level measurement on standard products has been conducted. Experiments were done on typical ST batches for 120, 90, and 65 nm nodes. KLA-Tencor SpectraCD SE system is used to collect and analyze line critical dimensions and profiles. A systematic correlation with Scanning Electron Microscope (SEM) is done, completed by a cross section analysis. The study also takes into account lithography defect anlysis using a specific targets with intentionally generated process failures. Our objective is to determine the sensitivity window of such measurment technique to process defect and marginal process conditions. We show that KLA-Tencor SpectraCD allows a full reconstruction of the line profile - as well as the film stack underneath it - with values that are in agreement with production control. Cpm values obtained on products demonstrate that SE based scatterometry fulfils all requirements to be integrated in a production envrionemnt and provides suitable metrology for advanced lithography process monitoring.

Electron beam direct write process development for sub 45nm CMOS manufacturing

Electron Beam Direct Write (EBDW) lithography represents a low cost and a rapid way to start basic studies for advance devices and process developments. Patterning for sub-45nm node technology requires the development of high performance processes. Different alternatives for the improvement of EBDW lithography are investigated in this paper for the ASIC manufacturing on 300mm wafer size. Among them, process development has been tuned for clear field equivalent level to improve both line width roughness by monitoring post applied bake conditions, and both process window by specific design correction. Concerning dark field level, process resolution has been improved by a shrinkage technique.

3D features analysis using spectroscopic scatterometry

Spectroscopic scatterometry is an optical metrology technique based on light scattering aiming at measuring geometrical dimensions, such Critical Dimension (CD) but also height or depth, side-wall angle and even more tiny details in a line profile. Scatterometry tool measures and analyzes the spectrum scattered or diffracted from a periodic target patterned on a wafer. Scatterometry is strongly considered as an alternative or as a complementary technique to CDSEM for 90 nm and below technology nodes. Like other optical metrology techniques, scatterometry measurements are rapid, non-destructive and highly repeatable. Actual tools have been assessed for dense to semi-isolated lines CD metrology and profiling. Developments are now targeting hole measurement. 2D-scatterometry (scatterometry on 3D patterns) becomes mature and begins to be used in advanced fab for CD control after lithography. This paper focuses on the capability of the spectroscopic scatterometry method to determine holes features and to try to give theoretical limits of method. Scatterometry uses an optical tool for spectra recording and a software tool including an advanced electromagnetic simulator and an optimization loop for data extraction. The first part of this study reports on the influence of bi-periodic structures in the experimental analysis of holes measurements. Then a limitation in holes density is defined. The second part of this study is a theoretical analysis based on simulation of the sensitivity of scatterometry with respect to various holes parameters. Following parameters are generally taken into account: holes diameter, holes ellipticity (elliptical ratio), holes roundness, holes depth and tilt angle for non-circular holes. We determine the respective influence of these parameters on ellipsometric spectra.

Shaped e-beam lithography integration work for advanced ASIC manufacturing: progress report

For the sub-90 nm node integrated circuits design rules, ITRS forecasts require minimal gate line width down to 55-35 nm. To reach such aggressive targets, most advanced optical lithography tools combined with all reticle enhancement techniques will be requested inducing important manufacturing cost and mask cycle time increase. In order to address prototyping market and reduce fabrication cost, shaped electron beam lithography may represent a technological alternative for cost reduction due to its high resolution and potential throughput capabilities. This paper is focused on the integration of this technology in standard ASIC plant, including resist process and overlay capabilities.

Manufacturing concerns for advanced CMOS circuit realization EBDW alternative solution for cost and cycle time reductions

The introduction of Electron Beam Direct Write lithography into production represents a challenging alternative to reduce cost and cycle time increase induced by the introduction of new generation nodes. This paper details the development work performed to insert transparently direct write lithography process and alignment strategies into CMOS process flows. Finally, this interchangeability between E-Beam and optical lithography steps offers a complete flexibility for device architecture validation and allowed the development of a complete low cost 65nm platform including low-power and general-purpose applications.

Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction

With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.

Strategies of optical proximity correction dedicated to chromeless phase lithography for 65 and 45 nm node

This paper shows the capability of chromeless phase lithography (CPL) and is particularly focused on different strategies for optical proximity corrections (OPC). A chromeless phase database is easily obtained from the original layout by changing the chromium pattern into a phase pattern. However, a specific optical proximity correction has to be applied due to the phase effect and the high transmission of the mask. Mask Error Enhancement Factor (MEEF) and process window for CPL technology have been estimated through wafer exposures. Moreover, various optical proximity correction strategies have been explored through a comparison between phase and chromium features such as hammerhead, zebra and scattering bars 1,2. Indeed, depending on the density of the pattern, we can improve the contrast and the process window by changing the local transmission. The transmission can be controlled by the addition of sub resolution chromium feature such as zebra chromium transverse features on the line for dense pattern, or chromium scattering bars in the space for a sparse pattern, or chromium patches on the line end. From 65 nm node measurements and 45 nm node simulations, the authors will then present the most effective sub resolution pattern to implement.