Sergei V. Postnikov

Critical dimension control in optical lithography

The exposure tool used for integrated circuit (IC) fabrication is critical to improving the packing density and transistor speed of the circuits. In addition to increasing resolution, which improves packing density and transistor speed, the exposure tool is also expected to provide tight linewidth control across the chip. Across chip linewidth variation (ACLV) has a significant influence on circuit speed. The allowed ACLV is usually assumed to be about 10% of the nominal linewidth. Therefore, just a few nanometers in linewidth variation may significantly impact IC performance. Contributions to the CD variation across chip and wafer due to lithographic sources of error are discussed in this paper. CD control afforded by future optical lithography tools is estimated using Monte Carlo aerial image simulations by making reasonable assumptions about the performance of the future tools and mask CD control. The impact of reticle enhancement technologies on ACLV is evaluated. The main sources of CD error can be identified. This approach will help define the path to improving CD control. The technique described was tested using data from the current generation of technology, and reasonable agreement between predicted and observed CD variation was obtained.

Evaluation of the critical dimension control requirements in the ITRS using statistical simulation and error budgets

To evaluate the ability to achieve the CD control requirements listed in the International Technology Roadmap for Semiconductors (ITRS) and to set error budget targets for focus, dose, PEB temperature uniformity, and mask CD control, statistical lithography simulation was used. A statistical model of total CD control, including the effects of intrafield and interfield error sources, was developed. The exposure tool settings such as wavelength, NA and partial coherence, focus and dose error budgets, lens aberration levels, mask type and pattern pitch values were determined for each node. Monte Carlo simulation was used to predict the CD error due to intrafield dose and focus errors. The contribution to CD error due to the mask was determined using mask CD control values in the ITRS and a calculated MEEF value at various defocus settings. The contribution to CD error due to PEB temperature variations, across wafer dose variations, and variation of aberrations and flare within the exposure field was also simulated. To meet ITRS CD control targets for 130-nm and 90-nm nodes, an alternating PSM mask is required along with a larger CD printed in resist than indicated in the ITRS. Meeting ITRS CD control requirements for 65-nm node and beyond not possible using assumptions detailed here, even with a near ideal APSM. The simulations predicted that if a relaxed pitch and a larger CD in resist were used at the 32nm node, 193nm immersion lithography in combination with a nearly ideal alternating PSM might provide CD control that is comparable to that obtainable using extreme ultraviolet lithography (EUVL).

Monte Carlo method for highly efficient and accurate statistical lithography simulations

Recent years have shown a strong increase in the use of statistical lithography error analysis for process tuning and in making technology choices. Simulation has shown it can play an important role in this area by accurately predicting experimental critical dimension (CD) distributions. Earlier statistical lithography simulation work was based on the Response Surface Methodology. The response surface is built by simulating CD dependence on input lithography process variables of interest such as focus, dose, mask CD, resist thickness, etc. The process parameters are then sampled from the Gaussian distribution to generate the distribution of the resulting resist CDs. When a large number of input parameters are being considered in order to describe the important experimental variations, the computational runtime is rapidly increased due to the requirements to fully simulate an (N+1)-dimensional response surface, where N is the number of input parameters. The work we present here has improved the speed of statistical lithography simulations through the use of Monte Carlo technique. With this technique, the runtime of the simulations is independent of the number of input parameters. The technique can be used for 1D or 2D simulations. We present results benchmarked with 130 nm process data showing the usefulness, runtime improvements and accuracy of this method. We have also used Variable Threshold Resist model (VTRM) in conjunction with the Monte Carlo technique. VTRM was calibrated against experimental focus-exposure matrices at varying line width and pitch. The use of VTRM greatly improves the accuracy of the statistical results by the virtue of establishing a good fit to the experimental data, which can be quantified by the root mean squares of residuals. VTRM also significantly speeds up the computation, since it uses only aerial image calculation as opposed to full resist modeling. Simulation results produced by using VTRM closely match the experimental results through a range of pitches, mask line widths and various illumination conditions.

Lithography: Concepts, Challenges and Prospects

Publisher Summary This chapter discusses that lithography is a key technology enabling the continued miniaturization of integrated circuits. An overview is presented of all the important aspects of lithography. Some basic scaling equations governing the theory of optical lithography are presented, but the chapter focuses on describing the practical challenges in applying lithography for integrated circuit manufacturing. Practical aspects of pattern layout, exposure tool design, masks, lens design, CD control, overlay control, resists, substrate control, simulation, optical proximity correction, phase shift masks, cost of ownership, and emerging lithographic techniques are described in detail.

Re-evaluating simple lambda-based design rules for low-K1 lithography process control

Due to the continuing decrease of the Rayleigh lithographic K1 factor used in advanced semiconductor technology, the non- linearity between designed and printed circuit images continues to increase. This increasing non-linearity has significant implications for the layout design rules with advanced technology. Recently, industry pundits have speculated that lithographic K1 factors can go far below current value. This paper aims to understand the impact of low K1 lithography upon a set of basic, company independent, layout design rules, the lambda based rules proposed by Mead and Conway. The results show that even with the use of aggressive optical proximity correction (OPC) techniques, significant changes in layout design rules will have to be made in order to extend lithographic capability to the low K1 regime.

Process latitude measurements and their implications for CD control in EUV lithography

We have exposed 10 wafers on the Engineering Test Stand (ETS), the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The EUV reflective mask was fabricated in-house using a Ta-based absorber stack on Mo/Si multilayers. The printed wafers contained different line sizes and pitches, line-end shortening measurement structures, contact holes, and patterns for estimating absorber defect printability. The depths of focus of each feature are typically 2 um due to the small NA of the scanner, and these should decrease by at least a factor of 6.25 as the NAs increase to 0.25. The data from measurements of line size through pitch and line-end shortening test structures indicate that both 1D and 2D optical proximity correction will be required. Defects that are either notches in or protrusions from absorber lines are the first to print, and they begin to print when they reach approximately 15~nm (1X) in size. This size threshold is in accordance with the 2003 ITRS specifications. We also report the first printing of SRAM bitcells with EUV lithography.

Process, design and optical proximity correction requirements for the 65nm device generation

The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.

Lithographic process window analysis by statistical means

In this paper, we discuss a methodology for characterizing and comparing the lithographic process from the CD control point of view. In contrast to the traditional method of exposure latitude vs. depth of focus widely used in lithography, we use the statistical line width variation Cpk, and Cp as the measures of the lithographic process performance and capability. We have developed a software package called Megastat, which estimates CD variation based on experimental focus and exposure matrix (Bossung Curves) and assumed or independently measured focus and dose stochastic behavior. A similar approach was considered in. The impact of focus and dose control on across chip line width variation (ACLV) and across wafer line width variation (AWLV) was quantified with Megastat and compared to the experimentally obtained CD control for a particular 248nm lithographic process for the 130nm technology node. The statistical approach utilized in the Megastat software produced a very good match with the experimental results, which confirmed the usefulness of the statistical approach to characterizing the lithographic processes. We have additionally devised methods for decoupling and determining the actual experimental statistical variations inherent in lithographic processes. These methods allow the input 1 sigma variations for the statistical window analysis to be accurately determined. The usefulness of these methods will also be shown.

Impact of optimized illumination upon simple lambda-based design rules for low-K1 lithography

The use of low K1 lithography to extend Moores Law has been shown to have large implications for random logic design rules. In this work we are continuing the analysis of process control and design rule implications of low K1 lithographic systems to include highly optimized illumination and reticle enhancement conditions. Recent 248nm and 193nm lithography results have shown considerable improvements in two-dimensional pattern transfer linearity from optimized off-axis illumination. Due to the public unavailability of leading-edge layout rules (because of their extremely proprietary nature), we are applying our analysis to the simple lambda based design rule system of Mead and Conway. We analyze the impact of K1 and optimization method by comparing the (normalized) area of a typical SRAM bitcell redesigned according to these lambda based rules. The area of the bitcell strongly depends upon the design rules required for each enhancement technique and K1 factor to achieve a manufacturable cell. These area comparisons allow for easy viewing of the cost of pursuing different low K1 strategies. The results of this work are mainly generated from simulation but are backed by experimental verification from recent 193nm tool and process developments.

MEV as a new constraint for lithographers in the sub-100-nm regime

Mask error factor (MEEF) is a commonly used metric in lithography. This parameter gives a good indication of the impact of intra-mask CD variation on the wafer. Unfortunately, MEEF is useless to anticipate the CD variation on the wafer induced by Mask Mean-To-Target variation (MMT). Currently, MMT error is compensated by adjusting the exposure dose. This paper presents the concept of MEV (MEEF Energy-latitude Variation) which is defined by the equation δCDwafer=MEV *δMMT after the dose compensation in a similar way to the MEEF concept. A simple expression for MEV will be presented which shows that the MEV factor is proportional to the variation of the product of EL*MEEF through the population. Using 65nm logic gate level, MEV experimentally shown to be non-zero, and roughly ½ times MEEF factor, which is of course non-negligible in sub 100nm regime. Based on aerial image simulation, pure optical effects are responsible for about 40% of the MEV, which gives a slight predominance of the resist part. Finally, the possibility of reducing the MEV factor by compensating for MTT variation not only by dose but also by illumination settings change is discussed. This will give the basis for an Advanced Process Control (APC) algorithm for the future generations.