Daniel J. Esteban

Application of quadrature mirror filters to split band voice coding schemes

This paper deals with applications of Quadrature Mirror Filters (QMF) to coding of voice signal in sub-bands. Use of QMFs enables to avoid the aliasing effects due to samples decimation when signal is split into sub-bands. Each sub-band is then coded independently with use of Block Companded PCM (BCPCM) quantizers. Then a variable number of bits is allocated to each sub-band quantizer in order to take advantage of the relative perceptual effect of the quantizing error. The paper is organized as follows: - First, splitting in two sub-bands with QMFs is analysed. -Then, a general description of a splitband voice coding scheme using QMFs is made. -Finally, two coding schemes are considered, operating respectively at 16 KBps and 32 KBps. Averaged values of S/N performances are given when encoding both male and female voices. Comparisons are made with conventional BCPCM and CCITT A-Law. Taped results will be played at the conference.

32 Kbps CCITT Compatible split band coding scheme

This paper deals with the application of the SVCS (Split band Voice Coding Scheme) concept to the coding of a PCM channel at half the rate of the presently used 64 kbps CCITT standard. This 32 kbps coder is shown to meet the specifications as recommended by the CCITT for a PCM channel operating at 64 kbps (8kHz sampling, 8 bits/sample A-Law). In addition, channel performances have been evaluated with and without transmission errors for different types of signals ranging from tones and modem signals to voice signals. It has been observed that transparency and apparent channel performances are not affected and that the behavior of the proposed 32 kbps is considerably less affected by transmission errors than the 64 kbps. Examples of taped results assuming different error rates on a voice signal with both the 32 kbps SVCS and the 64 kbps A-Law will be played at the conference.

16kbps Real time QMF sub-band coding implementation

The availability of medium performance microprocessors, in conjunction with different concepts to generate real time efficient signal processing software on microprocessors without hardwired multipliers, allows the real time implementation of sub-band voice compression algorithms. This paper deals with the implementation of a 16kbps (8kHz, 2 bits per sample) 8 sub-band coder assuming a bank of 40 tap QMF decimator and interpolator filters, an adaptive allocation of the bits resource based on channels activity and a straigth block PCM coding of the decimated samples. The paper focuses on the implementation and software techniques which were used to achieve a complete sub-band coder with about 1.3 million of instructions per second on a processor with a 16 bits instruction and data flow.

Design and evaluation of parallel quadrature mirror filters (PQMF)

Quadrature mirror filters (QMF) have been proposed in /1/, and are now widely used in digital sub-band coding of speech. The standard approach to the QMF splitting/reconstruction of a signal is based on a tree arrangement of half-band QMF filters. In this paper, we show that, assuming a proper design, a parallel implementation of the QMF filter bank (PQMF) is much more efficient than the tree implementation. In the first part of the paper, the basic tree approach is briefly reviewed. Than the parallel filter bank structure is introduced, the equations for alias-free reconstruction are derived and solved. It is shown that the parallel approach can drastically be simplified by truncating the so computed impulse responses. The effects of this truncation have been experimentally evaluated and some rules of thumb have been established for optimum truncation order. An example of design is given to illustrate the proposed method.

Multirate sub-band coder with embedded bit stream: Application to digital TASI

Application of sub-band coders to Time Assignement Speech Interpolation systems (TASI) is discussed. After a short review of standard optimum allocation of bits for one single voice port, the extension to multiports is discussed and is shown to present significant drawbacks. A new TASI approach with embedded bit stream is then proposed. The output of the multirate speech compressor has an embedded bit stream, i.e. accepts bit deletion and insertion for dynamic rate conversion /1/. This property is of high importance in a digital communication network, since it allows the bit stream to be flagged at any overloaded node without tandeming or freeze-out. The imbedded operation is obtained by taking advantage both of the sub-band coder architecture and of the dynamic bit allocation. So as to illustrate the method, a multirate version of a sub-band coder has been designed to operate at different rates: 8,16,24,32 kbps, providing a full range of quality from communications quality to toll quality.

16 Kbps sub-band coder incorporating variable overhead information

In this paper, a new block companded quantization method involving a variable rate strategy for transmission of the overhead information is proposed and applied to 16 kbps sub-band coding. In the first part of the paper, the basic sub-band coding technique with fixed rate for transmission of the block quantizer overhead information is reminded. Then, two algorithms for variable rate strategy are described, which are based on a classification of processed blocks into stationary and transient ones. These algorithms are incorporated into three sub-band coders operating at 16 kbps: a 16 sub-band and an 8 sub-band coders based on a uniform analysis, and an 8 sub-band coder based on a non-uniform analysis according to the articulatory index. The evaluation of the coders is based on comparative listening tests, and shows the efficiency of the variable rate strategy.

A 4800 bps voice excited predictive coder (VEPC) based on improved baseband/Sub-bands filters

A Voice Excited Predictive Coding architecture (VEPC) has been recently proposed allowing to compress digital speech at bit rates of 9600/7200 bps with a telephone quality. In order to decrease the bit rate down to 4800 bps, while preserving a same level of quality, several improvements of the processing blocks have been considered: · an adaptive pre-emphasis of the predictor coefficients, · a five to one decimation of the residual signal to reduce the residual baseband to 800 Hz, · a parallel implementation of the sub-bands splitting-reconstruction. This paper deals with the improvements as well as the implementation aspects. Taped results will be played at the conference.

Low‐bit‐rate voice transmission based on transversal block coding

A low‐bit‐rate voice coding scheme, in the range of 10 to 20 KPS, based on predictive transversal block coding is described. This voice coding scheme assumes the use of short‐ and long‐term linear prediction and an optimum PCM/DPCM block companding quantizer which ensures the same dynamic as a standard PCM companded law. It accommodates various data rates by simply modifying the number of bits allocated to the quantizer. Examples based on 8‐kHz sampling rate and data rates of 8 to 16 KBPS are investigated. It is shown that a two‐bit coding scheme at 20 KBPS provides a quality and intelligibility which is quite the same as the standard A‐law 84‐KBPS coding scheme and that with one‐bit coding at 12 KBPS the quality degradation is practically not noticeable in telephony applications. Tape recordings of the investigated cases will be played at the conference.

Dynamic assembling application to signal processing to generate time efficient sum of multiplications

In this paper, the application of dynamic assembling to the generation, on a sequential type processor of the basic time efficient instructions set required to perform any sum of multiplications, is presented. The considered procedure is based on the use of elementary machine instructions (such as add or subtract register, shift register) applied to integer coefficients represented in their minimal canonical signed-digit form. Examples of dynamic assembling application either at assembling time or at execution time, as well as results, are discussed. It is shown that improvement [expressed in terms of machine cycles reduction] can be as large as 20 providing thus an effective multiplication rate of the order of 1 to 2 million per second on a processor with an instruction cycle of 100 ns.

Real time signal processing software for multiplierless microprocessors

Different concepts to generate real time efficient signal processing software for microprocessors without hardwired multiplier have been recently introduced for application to digital signal filtering with fixed coefficients [1]. These approaches are extended to the generation of time efficient code for the computation of signal prediction (or filter with variable coefficients), autocorrelation (or correlation) as required in the area of digital speech processing. The reference processor, which has been specifically designed to allow both dynamic on-line code generation, is composed of a 16-bit ALU built around the Am2900 4-bit slice general purpose micro-processor which performs with a same level of accuracy as any general purpose floating point scientific program for the considered examples.