Daniel Llamocca

A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization

We introduce a dynamically reconfigurable framework for implementing single-pixel operations. The system relies on a multiobjective optimization scheme that generates Pareto-optimal realizations in the power/energy-performance-accuracy (PPA/EPA) spaces. The Pareto-optimal realizations and their PPA/EPA values are stored in DDR-SDRAM and can be chosen dynamically to meet time-varying constraints. Results are shown in terms of power, accuracy (peak signal-to-noise ratio) of the resulting image, and performance in frames per second. Dynamic PPA/EPA management is implemented using dynamic partial reconfiguration and dynamic frequency control.

Separable FIR Filtering in FPGA and GPU Implementations: Energy, Performance, and Accuracy Considerations

Digital video processing requires significant hardware resources to achieve acceptable performance. Digital video processing based on dynamic partial reconfiguration (DPR) allows the designers to control resources based on energy, performance, and accuracy considerations. In this paper, we present a dynamically reconfigurable implementation of a 2D FIR filter where the number of coefficients and coefficients values can be varied to control energy, performance, and precision requirements. We also present a high-performance GPU implementation to help understand the trade-offs between these two technologies. Results using a standard example of 2D Difference of Gaussians (DOG) filter indicate that the DPR implementation can deliver real-time performance with energy per frame consumption that is an order of magnitude less than the GPU. On the other hand, at significantly higher energy consumption levels, the GPU implementation can deliver very high performance.

Partial reconfigurable fir filtering system using distributed arithmetic

Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.

Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing

There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints on energy, performance, and accuracy. The generation of real-time constraints will significantly expand the applicability of dynamically reconfigurable systems to new domains, such as digital video processing. We develop a dynamically reconfigurable 2D FIR filtering system that can meet real-time constraints in energy, performance, and accuracy (EPA). The real-time constraints are automatically generated based on user input, image types associated with video communications, and video content. We first generate a set of Pareto-optimal realizations, described by their EPA values and associated 2D FIR hardware description bitstreams. Dynamic management is then achieved by selecting Pareto-optimal realizations that meet the automatically generated time-varying EPA constraints. We validate our approach using three different 2D Gaussian filters. Filter realizations are evaluated in terms of the required energy per frame, accuracy of the resulting image, and performance in frames per second. We demonstrate dynamic EPA management by applying a Difference of Gaussians (DOG) filter to standard video sequences. For video frame sizes that are equal to or larger than the VGA resolution, compared to a static implementation, our dynamic system provides significant reduction in the total energy consumption (>30%).

A dynamically reconfigurable parallel pixel processing system

We describe a dynamically reconfigurable image processing system that reaches real time video processing performances despite reconfiguration time overhead. The system is composed of reconfigurable pixel processing units set to process several pixels in parallel. We present a scheme for optimizing a LUT-based architecture by directly mapping it into the Xilinx FPGA CLB primitives. Internally controlled Dynamic Partial Reconfiguration is to modify the LUT values at run-time without stalling the overall operation. The combination of optimized implementations with CLB primitives and Dynamic Partial Reconfiguration leads to multifunctional, area-efficient, and highperformance realizations of LUT-based pixel processing systems. We present results from a dynamically reconfigurable high-performance LUT-based image/video processing system. Experimental measurements show that the system achieves speeds of 226Mbps with small resource utilization. The architecture can dynamically reconfigure the image processing operation at each new frame and still reach real-time video processing speeds (640×480 graylevel frames). We also evaluate the effect that increasing partial reconfiguration rates have on the systems overall performance.

A dynamically reconfigurable computing model for video processing applications

We introduce an idealized dynamically reconfigurable computing model that is suitable for applications in video processing applications. Dynamically reconfigurable computing is characterized by a dynamic data path which has been made possible with the partial reconfiguration feature available in modern FPGA devices. Dynamically reconfigurable computing design leads to a multi-objective optimization model with constraints on power, performance and resources. We provide a review of recent reconfigurable computing applications reported by different groups and propose a new model for dynamically reconfigurable video processing applications. We provide model measurements for reconfiguration time overhead, static and reconfiguration power consumption.

Cell-Based Architecture for Adaptive Wiring Panels: A First Prototype

Wepresent a first prototype for developing the concept of amanifold of adaptive wiring cells connected as a single overall adaptive wiring panel. Themain use of the adaptive wiring panel is related to affordable plug-and-play space applications. A reconfigurable switch fabric enables dynamic routing of signals and power; thus, power, digital, and analog signals can be routed for space systems. This concept can also be applied to terrestrial applications such as aircraft wiring and ground-based systems. The adaptive wiring panel is a manifold of adaptive wiring cells cast as a single overall panel. The panel is a pegboard-like structure, which does not articulate specific sockets, but rather provides a continuous grid of contact pads and mechanical mounting holes. Implementation is based on three basic elements: 1) cell units, which are minimum independent units of the adaptive wiring panel, each with interconnections and links with other cells to form the switch fabric by which wewire components to each other; 2) a cell management unit, which talks independently with all cell units and manages the wiring path and panel switch connections; and 3) modules that provide the components to be wired.

A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters

Many DSP, image and video processing applications use Finite Impulse Response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-computed, fixed-point realizations of different digital filters. Our platform relies on the use of Distributed Arithmetic blocks, mapped to the specific LUTs of the underlying FPGA. Dynamic reconfiguration of the coefficients is limited to changing a small number of relevant LUT contents, while leaving the rest of the architecture intact. We investigate the dynamic system throughput as a function of the dynamic reconfiguration rate.

A unified and pipelined hardware architecture for implementing intra prediction in HEVC

The High Efficiency Video Coding (HEVC) standard can achieve significant improvements in coding performance over H.264/AVC. To achieve significant coding improvements in intra-predictive coding, HEVC relies on the use of an extended set of intra-prediction modes and prediction block sizes. This paper presents a unified hardware architecture for implementing all 35 intra-prediction modes that include the planar mode, the DC mode, and all angular modes for all prediction unit (PU) sizes ranging from 4 × 4 to 64 × 64 pixels. We propose the use of a unified reference sample indexing scheme that avoids the need for sample re-arrangement suggested in the HEVC reference design. The hardware architecture is implemented on a Xilinx Virtex 5 device (XC5VLX110T) for which we report power measurements, resource utilization, and the average number of required cycles per pixel.

Scalable Open-Source Architecture for Real-Time Monitoring of Adaptive Wiring Panels

The first prototype of an adaptive wiring panel was recently introduced that implemented a reconfigurable switch fabric that allows dynamic routing of analog, digital, and power signals for space system applications. In this paper, a complete redesign and reimplementation of the adaptive wiring panel system is considered to address issues associated with scalability, reliability, and real-time monitoring of the switching fabric. The new system is demonstrated using 48 cells as opposed to the six cells of the first adaptive wiring panel prototype. The hardware and software systems are open source, and recommendations are provided to support further extensions to the system.