G. Alonzo Vera

Partial reconfigurable fir filtering system using distributed arithmetic

Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.

A dynamically reconfigurable parallel pixel processing system

We describe a dynamically reconfigurable image processing system that reaches real time video processing performances despite reconfiguration time overhead. The system is composed of reconfigurable pixel processing units set to process several pixels in parallel. We present a scheme for optimizing a LUT-based architecture by directly mapping it into the Xilinx FPGA CLB primitives. Internally controlled Dynamic Partial Reconfiguration is to modify the LUT values at run-time without stalling the overall operation. The combination of optimized implementations with CLB primitives and Dynamic Partial Reconfiguration leads to multifunctional, area-efficient, and highperformance realizations of LUT-based pixel processing systems. We present results from a dynamically reconfigurable high-performance LUT-based image/video processing system. Experimental measurements show that the system achieves speeds of 226Mbps with small resource utilization. The architecture can dynamically reconfigure the image processing operation at each new frame and still reach real-time video processing speeds (640×480 graylevel frames). We also evaluate the effect that increasing partial reconfiguration rates have on the systems overall performance.

An Introduction to Reconfigurable Systems

Reconfigurability can be thought of as software-defined functionality, where flexibility is controlled predominately through the specification of bit patterns. Reconfigurable systems can be as simple as a single switch, or as abstract and powerful as programmable matter. This paper considers the generalization of reconfigurable systems as an important evolving discipline, bolstered by real-world archetypes such as field programmable gate arrays and software-definable radio (platform and application, respectively). It considers what reconfigurable systems actually are, their motivation, their taxonomy, the fundamental mechanisms and architectural considerations underlying them, designing them and using them in applications. With well-known real-world instances, such as the field programmable gate array, the paper attempts to motivate an understanding of the many possible directions and implications of a new class of system which is fundamentally based on the ability to change.

A dynamically reconfigurable computing model for video processing applications

We introduce an idealized dynamically reconfigurable computing model that is suitable for applications in video processing applications. Dynamically reconfigurable computing is characterized by a dynamic data path which has been made possible with the partial reconfiguration feature available in modern FPGA devices. Dynamically reconfigurable computing design leads to a multi-objective optimization model with constraints on power, performance and resources. We provide a review of recent reconfigurable computing applications reported by different groups and propose a new model for dynamically reconfigurable video processing applications. We provide model measurements for reconfiguration time overhead, static and reconfiguration power consumption.

A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing several arithmetic cores for parallel processing while supporting high numerical precision with finite logical resources. This paper introduces an arithmetic architecture that uses runtime partial reconfiguration to dynamically adapt its numerical precision, without requiring significant additional logical resources. The paper also quantifies the relationship between reduced logical resources and savings in power consumption, which is particularly important for FPGA implementations. Finally, our results show performance benefits when this approach is compared to alternative static solutions within bounds on the reconfiguration rate.

A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters

Many DSP, image and video processing applications use Finite Impulse Response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-computed, fixed-point realizations of different digital filters. Our platform relies on the use of Distributed Arithmetic blocks, mapped to the specific LUTs of the underlying FPGA. Dynamic reconfiguration of the coefficients is limited to changing a small number of relevant LUT contents, while leaving the rest of the architecture intact. We investigate the dynamic system throughput as a function of the dynamic reconfiguration rate.

Appliqué Sensor Interface Module Based on 90nm Rad- Hard Structured Application-Specific Integrated Circuit

Applique Sensor Interface Modules (ASIMs) provide a convenient implementation of the Space Plug-and-Play Avionics (SPA) standard for common spacecraft devices. ASIMs simplify the chore of interfacing to SPA by providing automatic support for the low-level physical interface, electronic datasheets, synchronization, and power management. ASIMs have been implemented in an array of technologies, including programmable logic devices. In this paper we describe the first ASIM design based in a radiation hardened by design (RHBD) structured application specific integrated circuit (S-ASIC) fabric, based on the IBM 90nm bulk CMOS process, leveraging one of the processes used in the trusted foundry. This implementation, capable of supporting either SPA-U (USB) or SPA-S (Spacewire), is expected to result in the most-compact and power-efficient rad-hard ASIM design yet implemented.

A dynamic computing platform for image and video processing applications

We present a dynamic computing platform that allows for rapid prototyping of image and video processing applications systems. Here, an Ethernet MAC is used to stream video in and out of the FPGA. The output video is also sent to a video port for display. The system features a simple way to specify the dynamic video processing modules that are going to be multiplexed in time. The dynamic control is user-specified in the embedded processors software routine. We test the platform on two video processing applications, where the systems overall performance is evaluated as a function of the reconfiguration rate.

An XUP–UNM educational platform: A dual-FPGA platform for reconfigurable logic

We present a new educational platform for teaching reconfigurable logic. The new platform includes two FPGAs, separate instruction and data buses, serial and parallel port connections, and extensive I/O connections for interfacing with other reconfigurable computing boards. The platform was successfully tested at the University of New Mexico, the University of Texas at Austin, the University of Texas at El Paso, and the West Point military academy. Online documentation details the entire design, fabricating, assembly, and testing phases. All design information is freely available online.

The impact of terrestrial radiation effects on the reliability of a smart grid

This paper analyzes the impact of terrestrial radiation effects on the reliability of a Smart Grid. The mechanisms of radiation effects on semiconductor devices are briefly introduced and mitigation techniques are presented. Since this is a new research area, the future directions in it are discussed.